3. Architecture Introduction

Classic analog computers typically featured a large central patch panel consisting of thousands of sockets by means of which computing elements were connected with each other using patch cables. This was very cumbersome, took a long time to manually program, was error prone, and did not allow for rapid program changes. Fortunately with the REDAC system these patch panels are finally relegated to museums where they belong.

This section provides a brief overview about the architecture of the Reconfigurable Discrete Analog Computer, in short REDAC. For a more extensive documentation, see Architecture Reference in the developers manual.

3.1. REDAC internals

REDAC is a complex system consisting of a plethora of inner, “nested” subsystems. At the lowest levels, these systems are either digital or analog, rendering the overall system as a hybrid computer. The vast majority of electronics in REDAC is analog compute circuitery and analog interconnection networks, the digital parts are in fact only a tiny fraction of administrative control structures, realized in heterogenous computer architectures (both embedded, digital switching network and server grade processors).

REDAC follows the black box approach of operational amplifier based computing. This means REDAC is a giant replacement for an arithmetic-logical unit (ALU) of a traditional digital processor. The analog computing elements of REDAC can carry out basic mathematical operations such as addition and multiplication, but they can carry out also advanced operations such as integration in time. They do so at high accuracy and completely continous in time and with continous values. This is an important property of the REDAC compute elements but also its interconnection network, in short CTCV (continuous time, continuous variable). For the analog network, this means that the connections between the analog computing elements within a REDAC system are not based on switched capacitors but instead on static (reconfigurable) switching matrices. Although a switched capacitor network could have simplified the actual hardware implementation, it would immediately invalidate the low energy footprint of the analogy compute paradigm.

3.2. The system matrix

When using an analog computer such as REDAC, one maps a mathematical set of equations onto an electronical circuit, also refered to as compute graph. When drawing the adjacency matrix of this graph, one can think of REDAC as a large interconnection matrix of size \(N^2\) with \(N\) compute elements at the edges, as illustrated in figure Fig. 3.1.

Fig. 3.1 Interconnection matrix with implicit summing capabilities (Note: in fact this figure shows a Single cluster).

This illustration should be understood as following: At the left side, there are computing elements which feed their output to a column of a matrix (this is called a fan-out). Each matrix element is real-valued and constant during analog computation time (this is conceptually called a potentiometer). One can imagine that each cell in the row subsequently holds the incoming compute result multiplied with the matrix value at that place. The figure shows a special kind of matrix which has the property of building the column sum, i.e. there is a fan-in happening which reduces the values by building a sum. There is then a 1:1 correspondence of columns and rows, i.e. in the simplest case row \(i\) feeds back to column \(i\) (monadic compute element) whereas the summing reduction is a bit simplistic for dyadic compute elements such as a multiplier which has (in theory at least, in REDAC exactly) two inputs which are supposed to be multiplied together.

This way, arbitrary connections between compute elements are possible (also refered to as all-to-all connectivity). In practice, however, REDAC allows only for sparse matrices, i.e. does not allow arbitrary connections between computing elements but only a tiny subset, with a sparsity beyond 90%. It is the job of the software to determine possible connections in order to make your mathematical problem fit on the computer.

3.3. Available compuing elements

In its final expansion stage, REDAC will have at the ballpark order of \(10^4\) computing elements of each kind, i.e. time integrators or multipliers. As already indicated above, addition is done “for free” by the interconnection scheme and thus available in much wider terms. In the same spirit, REDAC has at the order of at least \(10^5\) digital potentiometers (“weighted edges” in the interconnection graph) and many more non-weighted connections.

The computer will have about \(10^{3-4}\) analog-to-digital converters that can be routed to different computing elements, making flexible read-outs and debuggings of complex calculations possible.

The computer can be partitioned (time-sharing) by means which follow its hierarchical structure. Explaining this structure is beyond the scope of this short introduction. Instead, see section Section 14 to read more about the computer architecture.