18. Appendix

18.1. On the REDAC handbook

Most of the developers manual is about external documentation and material, in particular in the Software section but also the Hardware section. In contrast, this section is all about the REDAC manual itself, i.e. this documentation.

Technically, this is a documentation made with Sphinx. This allows a single reStructuredText base to be generated to interactive HTML websites as well as printable Latex PDFs.

18.1.1. About the versions

This documentation is versioned because it is improved over the time. You are currently viewing the document release v1.0-NN-g6a89d8f from Feb 19, 2025.

This version string is compatible to git describe, i.e. it reads something like v1.2.3-NN-g1234567. Here, v1.2.3 refers to the actual version whereas the suffix -NN-g1234567 is only there if this version is actually unnamed and follows after \(N\) commits after the versioned commit. The actual git shorthash is then suffixed after the -g.

18.2. List of Abbreviations

REDAC:

REConfigurable Analog Computer

Model-1:

Analog Paradigm Model-1 Computer

INT:

Integrator

INV:

Inverter

MULT:

Multiplier

DIMM:

Dual Inline Memory Module (Form factor for PCBs)

DDR:

Double Data Rate

DDA:

Digital Differential Analyzer

ACN:

Analog Compute Node

CN:

Compute Node

XBAR:

Crosspoint-switch / Crossbar-switch

AD:

Analog Digital

DA:

Digital Analog

AC:

Alternating Current

DC:

Direct Current

DC/DC:

DC-to-DC Converter (Power Supply)

DAC:

Digital to Analog Converter

MDAC:

Multiplying Digital to Analog Converter

ADC:

Analog to Digital Converter

DPT:

Digital Potentiometer

LSB:

Least Significant Bit

INL:

Integral Nonlinearity

DNL:

Differential Nonlinearity

VDD:

Drain Power Voltage

CMOS:

Complementary Metal-Oxide-Semiconductor

NMOS:

N-type Metal-Oxide-Semiconductor

PMOS:

P-type Metal-Oxide-Semiconductor

PCB:

Printed Circuit Board (Electronic Circuit Board)

IC:

Integrated Circuit or Initial Condition (depending on context)

OP:

Operating Mode

HALT:

Halting Mode

AMP:

(Operational) Amplifier

OPA:

Operational Amplifier

OPV:

Operational Amplifier

SMD:

Surface Mount Device

SOIC:

Small Outline Integrated Circuit

TSSOP:

Thin Shrink Small Outline Package

VSSOP:

Very Thin Shrink Small Outline Package

GBP:

Great Britain Pound

PT1:

First Order System with One Pole

GND:

Ground

RRO:

Rail to Rail Output

RRI:

Rail to Rail Input

CM:

Common Mode

SR:

Slewrate

GBW:

Gain Bandwidth (Product)

MUX:

Multiplexer

SPST:

Single Pole Single Throw

SPDT:

Single Pole Dual Throw

SPI:

Serial Peripheral Interface

M-Block:

Math Block

U-Block:

Voltage Block

C-Block:

Coefficient Block

I-Block:

Current Block

T-Block:

Topology Block

FDT:

Feedthrough

XTALK:

Crosstalk

PPV:

Perturbation Projection Vector

NP:

Nondeterministic Polynomial (Complexity Context)

P:

Polynomial (Complexity Context)

MPDE:

Multi-Time Partial Differential Equation

PDE:

Partial Differential Equation

pDGL:

Partial Differential Equation (German: Partielle Differentialgleichung)

DMA:

Direct Memory Access

HC:

Hybrid Controller

CU:

Control Unit

FlexIO:

Flexible Input and Output Peripheral (NXP)

GPIO:

General Purpose Input and Output Pins/Ports

CLK:

Clock Signal in Serial Interfaces (e.g., SPI)

MISO:

Master In, Slave Out (SPI Data Line)

MOSI:

Master Out, Slave In (SPI Data Line)

CS:

Chip Select (SPI Signal Line)

CNVST:

Conversion Start Signal of an ADC

PWM:

Pulse Width Modulation

CMP:

Comparator

18.3. Glossary

Backplane

A circuit board for housing and connecting carrier modules. The circuit board is the defining element of the iREDAC.

Carrier Module

A circuit board with DIMM slots and a VG strip: accommodates functional blocks and the CTRL block. This board is the defining element of the mREDAC and LUCIDAC.

Cluster

2x M-, 1x U-, 1x C-, 1x I-Block.

Carrier Module Prototype

1x Cluster and 1 CTRL-Block on a carrier module (=LUCIDAC, but not explicitly mentioned).

REDAC Carrier Module

3x Clusters and 1 CTRL-Block on a carrier module.

Functional Block

General term for M-, U-, C-, I-Block.

CTRL-Block

Control block: Interface between analog switching technology and digital computer.

Cluster

2x M-, 1x U-, 1x C-, 1x I-Block.

M-/U-/C-/I-Block

Mathematical or computing element, voltage coupling, coefficient, current coupling block.

Configuration, Circuit, Program

A data record that fully describes the analog interconnection of the REDAC. In the case of mREDAC, this primarily includes the UCI configuration, MIntConfig, and UBlockAltSignals. The UCI configuration can be represented in different matrix-like conventions or as a list of routes. See also specializations below, such as Irreducible Configuration or Cluster Configuration.

Interconnection Configuration

(As an alternative or German equivalent to “Configuration, Circuit, Program,” or at least a preferred term in the report) A specific interconnection between virtual or real computing elements. In current usage, it is unclear whether the configurations (e.g., initial values) of the elements are included, but they actually should be.

Cluster Configuration

A restriction of the configuration, e.g., to a single cluster.

Setting, Adjustments (but not: Configuration)

(Typically user-configurable runtime) settings in the Teensy that affect only the functionality of the Teensy itself and not the mREDAC configuration, i.e., the analog circuit. An example is the IP address of the Teensy.

Note: A setting is something the administrator sets. A config is something the user sets.

Lane

One of 32 lines through the UCI block: Leads from a U-block output through a DPT into an I-block input. As a data type, a lane is an integer in the range [0,31]. Also called a UCI lane.

The term “Lane Index” should be avoided; a lane always refers to an index.

Crosslane, short: Clane

One of 16 lines leading from the MBlock into the UBlock or from the IBlock back into the MBlock.

The term “clane index” should be avoided; a clane always refers to an index.

(Physical) Route

4-tuple: (uin, uout, cval, iout), where uin and iout are crosslanes and uout is a lane. cval is a coefficient value (float in the range [-20,+20]). There are a maximum of 32 routes in the mREDAC.

The iout value in a route is optional, as it can also lead to a virtual output (see below).

Compute Element, Element Description

A type description of a computing element, i.e., it describes the name and inputs/outputs but not the internal structure or behavior.

Element Name

By convention, the following computing element names are used in mREDAC: Mul, Int, Daq, Extout, Extin, Const, Pot.

Physical Compute Element

A computing element in the M-Block or C-Block, currently Int, Mult, and Coeff. The term refers to an abstract element, i.e., its type (structure/behavior) and not where it is located in the computer.

Virtual Compute Element

A computing element that cannot be physically localized cleanly, currently including External Inputs, External Outputs, DAQ Outputs, Constant Generators, and (arguably) Summators.

Stateful Compute Element

In general, compute elements are stateless. In mREDAC, only integrators and potentiometers have an internal state, and their types contain information such as IC, k0, or coeff-value.

Source, Output Compute Element

A monadic compute element with no output, i.e., a compute element with an empty input-port list and an output-port list containing only one element, conventionally called “source.” In mREDAC, these include External Input elements or constants.

All source elements in mREDAC are necessarily virtual computing elements.

Sink, Input Compute Element

The opposite of a source. In mREDAC, these are, for example, DAQ Output elements.

All sink elements in mREDAC are necessarily virtual computing elements.

Compute Element Port

Each computing element has a list of inputs and outputs. Entries in this list are called “ports.” By convention, monadic compute elements have only an “in” and an “out” port. Dyadic compute elements conventionally have “a” and “b” ports as outputs.

Assigned (Physical/Virtual) Compute Element

A computing element localized in the system: Typically, computing elements can be described by an index (in mREDAC) or by a hierarchical device-tree-like structure (in REDAC).

Virtual/Physical Assigned Compute Element Port

A combination of the above concepts, meaning a localized port of a specific computing element in the system. This concept also applies to virtual computing elements, which are simply numbered.

Virtual Route, also: Logical Connection

An unrouted route that connects two virtual (typically assigned) compute element ports.

Logical Route

A virtual route after Pick & Place, meaning it has, in the case of mREDAC, one or more candidate lanes assigned.

Auxiliary Block Configuration

Something like U-Block-Alt-Signals or MInt-Block configurations.

Irreducible Configuration

Description of the UCI matrix with as few degrees of freedom/variants as possible. This is either a description as a route list or as three U/C/I lists, all of which are input-centric.

Input-Centric Configuration, Output-Centric Configuration

Describes different ways to represent (linearize) UCI matrices. In the U-Block, the adjacency list of the U-Matrix is simultaneously an input-centric configuration and thus irreducible, as it is a simple list. In the I-Block, it is an output-centric configuration and thus a list of lists that can be represented as an input-centric one.

MBlock Setup

Describes which type of MBlocks sit in which MBlock slots. In the simplest case, this is a mapping of slot indices/coordinates to MBlock types.

Routing Error

Description of a result of a compilation step.

Physical Routing

Result of the P&R compilation step. The result includes not only physical routes but also a list of potential routing errors and the U-Alt-Block allocation.

SendEnvelope and RecvEnvelope

Generic envelope types for the JSON protocol. They always have an id (string, should be a UUID), a message type (string, from a list of supported messages), and a message type. A JSON schema should exist that covers all possible envelopes. The RecvEnvelope is similar.

Serialized Program, Exported Configuration

Dump of the data structure of a configuration in an appropriate data format such as JSON/YAML/etc. This should also include version information for reloading.

Structure Description (!= Hardware Description)

The description of the fundamental mathematical structure of an analog computer. In REDAC, for example, this includes the fact that signals pass through a coefficient and are then summed, meaning only fully multiplied terms can be computed, such as a*x + a*y but not a*(x+y). The structure description of an analog computer is static and does not change.

Required for the synthesis step of the compiler.

Behavioral Description (!= Hardware Description)

The description of the behavior of the analog computing elements and thus the analog computer. This corresponds to the mathematical modeling of a computing element. For example, an integrator is described by the temporal integral over its input signal. The behavioral description of a computing element is static and does not change.

Hardware Description (= Resource Description, = Hardware Configuration)

The list of all available computing elements (potentially implicitly defined by MBlock types) and the available interconnections (potentially implicitly defined by types and positions on backplanes, etc.).