Controller

Distributor

Warning

doxygennamespace: Cannot find namespace “dist” in doxygen xml output for project “hybrid-controller” from directory: ../doxygen/xml/

Nonvolatile configuration

Warning

doxygennamespace: Cannot find namespace “nvmconfig” in doxygen xml output for project “hybrid-controller” from directory: ../doxygen/xml/

Code Loaders

namespace loader

Functions

void reboot(): Just a little generic Teensy reboot routine.

Utilities

namespace utils

Typedefs

typedef enum utils::_dcp_ch_enable _dcp_ch_enable_t

typedef enum utils::_dcp_channel dcp_channel_t

typedef enum utils::_dcp_key_slot dcp_key_slot_t

typedef enum utils::_dcp_swap dcp_swap_t

typedef enum utils::_dcp_hash_algo_t dcp_hash_algo_t

typedef struct utils::_dcp_hash_ctx_t dcp_hash_ctx_t

typedef union utils::_dcp_hash_block dcp_hash_block_t

typedef enum utils::_dcp_hash_algo_state dcp_hash_algo_state_t

typedef struct utils::_dcp_handle dcp_handle_t

typedef struct utils::_dcp_hash_ctx_internal dcp_hash_ctx_internal_t

typedef struct utils::_dcp_work_packet dcp_work_packet_t

Enums

enum _generic_status

Values:

enumerator kStatus_Success

enumerator kStatus_Fail

enumerator kStatus_ReadOnly

enumerator kStatus_OutOfRange

enumerator kStatus_InvalidArgument

enumerator kStatus_Timeout

enumerator kStatus_DCP_Again

enum _dcp_ch_enable

Values:

enumerator kDCP_chDisable: DCP channel disable.

enumerator kDCP_ch0Enable: DCP channel 0 enable.

enumerator kDCP_ch1Enable: DCP channel 1 enable.

enumerator kDCP_ch2Enable: DCP channel 2 enable.

enumerator kDCP_ch3Enable: DCP channel 3 enable.

enumerator kDCP_chEnableAll: DCP channel enable all.

enum _dcp_channel

Values:

enumerator kDCP_Channel0: DCP channel 0.

enumerator kDCP_Channel1: DCP channel 1.

enumerator kDCP_Channel2: DCP channel 2.

enumerator kDCP_Channel3: DCP channel 3.

enum _dcp_key_slot

Values:

enumerator kDCP_KeySlot0: DCP key slot 0.

enumerator kDCP_KeySlot1: DCP key slot 1.

enumerator kDCP_KeySlot2: DCP key slot 2.

enumerator kDCP_KeySlot3: DCP key slot 3.

enumerator kDCP_OtpKey: DCP OTP key.

enumerator kDCP_OtpUniqueKey: DCP unique OTP key.

enumerator kDCP_PayloadKey: DCP payload key.

enum _dcp_swap

Values:

enumerator kDCP_NoSwap

enumerator kDCP_KeyByteSwap

enumerator kDCP_KeyWordSwap

enumerator kDCP_InputByteSwap

enumerator kDCP_InputWordSwap

enumerator kDCP_OutputByteSwap

enumerator kDCP_OutputWordSwap

enum _dcp_hash_algo_t

Values:

enumerator kDCP_Sha1: SHA_1.

enumerator kDCP_Sha256: SHA_256.

enumerator kDCP_Crc32: CRC_32.

enum _dcp_hash_digest_len

Values:

enumerator kDCP_OutLenSha1

enumerator kDCP_OutLenSha256

enumerator kDCP_OutLenCrc32

enum _dcp_work_packet_bit_definitions

Values:

enumerator kDCP_CONTROL0_DECR_SEMAPHOR

enumerator kDCP_CONTROL0_ENABLE_HASH

enumerator kDCP_CONTROL0_HASH_INIT

enumerator kDCP_CONTROL0_HASH_TERM

enumerator kDCP_CONTROL1_HASH_SELECT_SHA256

enumerator kDCP_CONTROL1_HASH_SELECT_SHA1

enumerator kDCP_CONTROL1_HASH_SELECT_CRC32

enum _dcp_hash_algo_state

Values:

enumerator kDCP_StateHashInit: Init state.

enumerator kDCP_StateHashUpdate: Update state.

Functions

void check_and_log_crash()

Logs out what has been captured by the Teensy CrashReport tooling, cf.

https://www.pjrc.com/teensy/td_crashreport.html

This can help to debug faults generated by the memory protection unit (MPU) such as null pointer references or other pointer arithmetics gone bad. In order to have this work, the microcontroller needs to do a “soft-reboot” which preserves the RAM content so the “post-mortem report” is available.

In order to understand the error codes, have a loook at the IMXRT1060 processor architecture manual, for instance at https://www.pjrc.com/teensy/DDI0403Ee_arm_v7m_ref_manual.pdf at page 611

static FLASHMEM void dcp_reverse_and_copy (uint8_t *src, uint8_t *dest, size_t src_len)

static FLASHMEM uint32_t dcp_get_channel_status (dcp_channel_t channel)

static FLASHMEM void dcp_clear_status ()

static FLASHMEM void dcp_clear_channel_status (uint32_t mask)

uint32_t DCP_WaitForChannelComplete(dcp_handle_t *handle)

static FLASHMEM uint32_t dcp_schedule_work (dcp_handle_t *handle, dcp_work_packet_t *dcpPacket)

static FLASHMEM uint32_t dcp_hash_update_non_blocking (dcp_hash_ctx_internal_t *ctxInternal, dcp_work_packet_t *dcpPacket, const uint8_t *msg, size_t size)

void dcp_hash_update(dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *msg, size_t size)

FLASHMEM void dcp_hash_process_message_data (dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *message, size_t messageSize)

FLASHMEM void DCP_HASH_Init (dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo)

FLASHMEM void DCP_HASH_Update (dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize)

FLASHMEM void DCP_HASH_Finish (dcp_hash_ctx_t *ctx, uint8_t *output)

FLASHMEM void dcp_init ()

FLASHMEM void prhash (unsigned char *h, int n)

FLASHMEM void demo_sha256 ()

FLASHMEM void demo_crc32 ()

FLASHMEM void hash (const uint8_t *msg, size_t msg_len, uint8_t *out_hash, dcp_hash_algo_t algo)

FLASHMEM void hash_sha256 (const uint8_t *msg, size_t msg_len, uint8_t *out_hash)

Computes the SHA256 sum of an arbitrary message (large memory segment).

Outputs an uint8_t[32]. Use for instance prhash(out_hash, 32) for a string representation.

FLASHMEM void hash_sha1 (const uint8_t *msg, size_t msg_len, uint8_t *out_hash)

inline uint32_t rotr(uint32_t x, uint32_t n)

inline uint32_t ch(uint32_t x, uint32_t y, uint32_t z)

inline uint32_t maj(uint32_t x, uint32_t y, uint32_t z)

inline uint32_t sigma0(uint32_t x)

inline uint32_t sigma1(uint32_t x)

Variables

std::array<uint32_t, 64> K = {0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5, 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc, 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da, 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967, 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3, 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070, 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3, 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2}

std::array<uint32_t, 4> H1 = {0x67452301, 0xEFCDAB89, 0x98BADCFE, 0x10325476}

struct _dcp_handle

Public Members

dcp_channel_t channel: Specify DCP channel.

dcp_key_slot_t keySlot: For operations with key (such as AES encryption/decryption), specify DCP key slot.

uint32_t swapConfig: For configuration of key, input, output byte/word swap options.

uint32_t keyWord[4]

uint32_t iv[4]

union _dcp_hash_block

Public Members

uint32_t w[128 / 4]: array of 32-bit words

uint8_t b[128]: byte array

struct _dcp_hash_ctx_internal

Public Members

dcp_hash_block_t blk

memory buffer.

only full blocks are written to DCP during hash updates

size_t blksz: number of valid bytes in memory buffer

dcp_hash_algo_t algo: selected algorithm from the set of supported algorithms

dcp_hash_algo_state_t state: finite machine state of the hash software process

uint32_t fullMessageSize: track message size

uint32_t ctrl0: HASH_INIT and HASH_TERM flags.

uint32_t runningHash[9]

running hash.

up to SHA-256 plus size, that is 36 bytes.

dcp_handle_t *handle

struct _dcp_hash_ctx_t

Public Members

uint32_t x[58]

struct _dcp_work_packet

Public Members

uint32_t nextCmdAddress

uint32_t control0

uint32_t control1

uint32_t sourceBufferAddress

uint32_t destinationBufferAddress

uint32_t bufferSize

uint32_t payloadPointer

uint32_t status

struct DCP_Type

DCP - Register Layout Typedef.

Public Members

volatile uint32_t CTRL: DCP control register 0, offset: 0x0.

uint8_t RESERVED_0[12]

volatile uint32_t STAT: DCP status register, offset: 0x10.

uint8_t RESERVED_1[12]

volatile uint32_t CHANNELCTRL: DCP channel control register, offset: 0x20.

uint8_t RESERVED_2[12]

volatile uint32_t CAPABILITY0: DCP capability 0 register, offset: 0x30.

uint8_t RESERVED_3[12]

volatile uint32_t CAPABILITY1: DCP capability 1 register, offset: 0x40.

uint8_t RESERVED_4[12]

volatile uint32_t CONTEXT: DCP context buffer pointer, offset: 0x50.

uint8_t RESERVED_5[12]

volatile uint32_t KEY: DCP key index, offset: 0x60.

uint8_t RESERVED_6[12]

volatile uint32_t KEYDATA: DCP key data, offset: 0x70.

uint8_t RESERVED_7[12]

volatile uint32_t PACKET0: DCP work packet 0 status register, offset: 0x80.

uint8_t RESERVED_8[12]

volatile uint32_t PACKET1: DCP work packet 1 status register, offset: 0x90.

uint8_t RESERVED_9[12]

volatile uint32_t PACKET2: DCP work packet 2 status register, offset: 0xA0.

uint8_t RESERVED_10[12]

volatile uint32_t PACKET3: DCP work packet 3 status register, offset: 0xB0.

uint8_t RESERVED_11[12]

volatile uint32_t PACKET4: DCP work packet 4 status register, offset: 0xC0.

uint8_t RESERVED_12[12]

volatile uint32_t PACKET5: DCP work packet 5 status register, offset: 0xD0.

uint8_t RESERVED_13[12]

volatile uint32_t PACKET6: DCP work packet 6 status register, offset: 0xE0.

uint8_t RESERVED_14[28]

volatile uint32_t CH0CMDPTR: DCP channel 0 command pointer address register, offset: 0x100.

uint8_t RESERVED_15[12]

volatile uint32_t CH0SEMA: DCP channel 0 semaphore register, offset: 0x110.

uint8_t RESERVED_16[12]

volatile uint32_t CH0STAT: DCP channel 0 status register, offset: 0x120.

uint8_t RESERVED_17[12]

volatile uint32_t CH0OPTS: DCP channel 0 options register, offset: 0x130.

uint8_t RESERVED_18[12]

volatile uint32_t CH1CMDPTR: DCP channel 1 command pointer address register, offset: 0x140.

uint8_t RESERVED_19[12]

volatile uint32_t CH1SEMA: DCP channel 1 semaphore register, offset: 0x150.

uint8_t RESERVED_20[12]

volatile uint32_t CH1STAT: DCP channel 1 status register, offset: 0x160.

uint8_t RESERVED_21[12]

volatile uint32_t CH1OPTS: DCP channel 1 options register, offset: 0x170.

uint8_t RESERVED_22[12]

volatile uint32_t CH2CMDPTR: DCP channel 2 command pointer address register, offset: 0x180.

uint8_t RESERVED_23[12]

volatile uint32_t CH2SEMA: DCP channel 2 semaphore register, offset: 0x190.

uint8_t RESERVED_24[12]

volatile uint32_t CH2STAT: DCP channel 2 status register, offset: 0x1A0.

uint8_t RESERVED_25[12]

volatile uint32_t CH2OPTS: DCP channel 2 options register, offset: 0x1B0.

uint8_t RESERVED_26[12]

volatile uint32_t CH3CMDPTR: DCP channel 3 command pointer address register, offset: 0x1C0.

uint8_t RESERVED_27[12]

volatile uint32_t CH3SEMA: DCP channel 3 semaphore register, offset: 0x1D0.

uint8_t RESERVED_28[12]

volatile uint32_t CH3STAT: DCP channel 3 status register, offset: 0x1E0.

uint8_t RESERVED_29[12]

volatile uint32_t CH3OPTS: DCP channel 3 options register, offset: 0x1F0.