tblock.cpp

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#include "teensy/tblock.h"
 
using namespace blocks;
 
const SPISettings TBlockHAL_V_1_0_X::F_CONNECTION_SPI_SETTINGS{
    4'000'000, LSBFIRST,
    SPI_MODE2 /* Chip expects MODE0, CLK is inverted on the way, but MOSI is not, thus CLK must be shifted */};
 
FLASHMEM TBlockHAL_V_1_0_X::TBlockHAL_V_1_0_X(bus::addr_t block_address)
    : TBlockHAL_Parent(block_address),
      f_set_mux_disable{bus::replace_function_idx(block_address, 5)},
      f_reset_mux_disable{bus::replace_function_idx(block_address, 6)},
      f_reset_connections{bus::replace_function_idx(block_address, 4)},
      f_connections{bus::replace_function_idx(block_address, 2), F_CONNECTION_SPI_SETTINGS},
      f_connections_sync{bus::replace_function_idx(block_address, 3)} {}
 
FLASHMEM void TBlockHAL_V_1_0_X::set_mux_disable() { f_set_mux_disable.trigger(); }
 
FLASHMEM void TBlockHAL_V_1_0_X::reset_mux_disable() { f_reset_mux_disable.trigger(); }
 
FLASHMEM uint8_t four_muxes_to_bit_sequence(Mux mux_0, Mux mux_1, Mux mux_2, Mux mux_3) {
  return mux_0.encode() | (mux_1.encode() << 2) | (mux_2.encode() << 4) | (mux_3.encode() << 6);
}
 
FLASHMEM bool TBlockHAL_V_1_0_X::write_muxes(std::array<Mux, 96> muxes) {
  // Order of muxes in function argument is [channel 8, 9, ..., 31]
  std::array<uint8_t, 24> data{};
  for (auto idx = 0u; idx < data.size(); idx++) {
    // Fill up MOSI buffer in reverse to ensure data arrives in correct order
    data[data.size() - 1 - idx] = four_muxes_to_bit_sequence(muxes[idx * 4 + 3], muxes[idx * 4 + 2],
                                                             muxes[idx * 4 + 1], muxes[idx * 4 + 0]);
  }
  auto success = f_connections.transfer(data.data(), nullptr, data.size());
  f_connections_sync.trigger();
  return success;
}
 
FLASHMEM bool TBlockHAL_V_1_0_X::reset_muxes() {
  f_reset_connections.trigger();
  return true;
#ifdef ANABRID_PEDANTIC
  std::array<uint8_t, 24> data{0};
  f_connections.transfer(data.data(), data.data(), data.size());
  return std::all_of(data.begin(), data.end(), [](auto value) { return value == 0; });
#else
  return true;
#endif
}
 
FLASHMEM TBlock::TBlock(TBlockHAL *hardware) : FunctionBlock("T", hardware), hardware(hardware) {
  classifier.class_enum = CLASS_;
}
 
FLASHMEM TBlock::TBlock() : TBlock(new DummyTBlockHAL()) {}
 
FLASHMEM
TBlock *TBlock::from_entity_classifier(entities::EntityClassifier classifier, bus::addr_t block_address) {
  if (!classifier or classifier.class_enum != CLASS_ or classifier.type != TYPE)
    return nullptr;
 
  if (classifier.version < entities::Version(1, 0, 2))
    // Version 1.0.1 was manufactured without any muxers on them :)
    return nullptr;
  if (classifier.version < entities::Version(1, 1))
    return new TBlock(new TBlockHAL_V_1_0_X(block_address));
  return nullptr;
}
 
FLASHMEM utils::status TBlock::config_self_from_json(JsonObjectConst cfg) {
  for (auto cfgItr = cfg.begin(); cfgItr != cfg.end(); ++cfgItr) {
    if (cfgItr->key() == "muxes") {
      auto res = config_self_from_muxes(cfgItr->value());
      if (!res)
        return res;
    } else {
      return utils::status("CBlock: Unknown configuration key");
    }
  }
  return utils::status::success();
}
 
FLASHMEM utils::status TBlock::config_self_from_muxes(const JsonVariantConst &muxes) {
  if (!muxes.is<JsonArrayConst>())
    return utils::status("TBlock: Muxes must be array");
  size_t idx = 0;
  for (const JsonVariantConst &mux : muxes.as<JsonArrayConst>()) {
    if (!mux.is<int>())
      return utils::status("TBlock: Mux must be int");
    int mux_value = mux.as<int>();
    if (mux_value < 0 || 4 <= mux_value)
      return utils::status("TBlock: Mux must be interval [0, 3]");
    f_data[idx] = Mux::from(mux_value);
    idx++;
  }
 
  return status::success();
}
 
FLASHMEM void TBlock::config_self_to_json(JsonObject &cfg) {
  Entity::config_self_to_json(cfg);
  auto muxes_cfg = cfg.createNestedArray("muxes");
  for (auto mux : f_data) {
    muxes_cfg.add(mux.index());
  }
}
 
FLASHMEM status TBlock::connect(uint8_t src_sector, uint8_t dst_sector, uint8_t sector_lane) {
  assert(src_sector < 4 && dst_sector < 4);
  auto dst_lane = dst_sector * 24 + sector_lane;
  if (f_used.test(dst_lane)) {
    // already used
    return status("TBlock output lane already used");
  }
 
  f_used.set(dst_lane);
  f_data[dst_lane] = Mux::from(src_sector);
  return status::success();
}
 
FLASHMEM void TBlock::reset(entities::ResetAction action) {
  Entity::reset(action);
  if (action.has(entities::ResetAction::CIRCUIT_RESET))
    reset_connections();
  if (action.has(entities::ResetAction::EVERYTHING))
    enabled = true;
}
 
FLASHMEM void TBlock::reset_connections() {
  // Note that the T-block always has connections, unless it is completely disabled (powered-off).
  // The least surprising default connection is to have signals stay in their originating cluster.
  f_used.reset();
  f_data = {Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D,
            Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D,
            Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D,
            Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D,
            Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D,
            Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D,
            Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D,
            Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D, Mux::A, Mux::B, Mux::C, Mux::D};
}
 
FLASHMEM status TBlock::write_to_hardware() {
  RETURN_IF_FAILED(Entity::write_to_hardware());
  if (!hardware->write_muxes(f_data))
    return status("Error writing mux settings to hardware.");
  if (enabled)
    hardware->reset_mux_disable();
  else
    hardware->set_mux_disable();
  return status::success();
}
 
FLASHMEM bool TBlock::is_enabled() const { return enabled; }
 
FLASHMEM void TBlock::set_enabled(bool enabled_) { enabled = enabled_; }
 
FLASHMEM status Router::route_cluster(SignalId output, SignalId input) {
  auto output_carrier = output.cluster.carrier;
  auto input_carrier = input.cluster.carrier;
  assert(output_carrier == input_carrier);
 
  if (output.id < 8)
    return status(output == input);
 
  // use T-Block inside carrier board
  auto output_sector_lane = output.id % 24;
  auto input_sector_lane = input.id % 24;
 
  if (output_sector_lane != input_sector_lane)
    return status("Connections inside carrier only allowed between same lane indices!");
 
  auto tblock = find_carrier_t_block(input_carrier);
  return tblock->connect(output.cluster.id, input.cluster.id, input_sector_lane);
}
 
FLASHMEM status Router::route_carrier(SignalId output, SignalId input) {
  auto output_carrier = output.cluster.carrier;
  auto input_carrier = input.cluster.carrier;
  if (output_carrier == input_carrier) {
    return route_cluster(output, input);
  }
 
  auto output_stack = output_carrier.stack;
  auto input_stack = input_carrier.stack;
 
  auto output_carrier_block = find_carrier_t_block(output_carrier);
  auto input_carrier_block = find_carrier_t_block(input_carrier);
 
  // Can only use lanes 8 .. 16 in cyclic connection inside one cluster
  if (8 <= output.id && output.id < 16) {
    bool short_loop = stack_is_long_loop.find(output_stack) == stack_is_long_loop.end();
    size_t loop_size = short_loop ? 3 : 6;
    size_t carrier_offset = output.id < 12 ? 1 : loop_size - 1;
    size_t next_carrier = (output_carrier.id + carrier_offset) % loop_size;
 
    // right short loop correction
    if (output_carrier.id >= 3)
      next_carrier += 3;
 
    CarrierId wired_carrier = CarrierId::from(input_stack.id, static_cast<uint8_t>(next_carrier));
 
    if (wired_carrier != input_carrier)
      return status("Connections between lanes [8, 15] are hard wired to different carrier");
 
    int lane_offset = output.id < 12 ? 4 : -4;
    auto wired_lane = output.id + lane_offset;
    if (wired_lane != input.id)
      return status("Output connections between lanes [8, 15] are hard wired to different input lanes");
 
    auto output_sector_lane = output.id % 24;
    auto input_sector_lane = input.id % 24;
 
    status result = status::success();
    result.attach(output_carrier_block->connect(output.cluster.id, 3, output_sector_lane));
    result.attach(input_carrier_block->connect(3, input.cluster.id, input_sector_lane));
    return result;
  }
 
  if (16 <= output.id && output.id < 32) {
    if (output.id != input.id)
      return status("Carrier connections only allowed between common lanes");
 
    status result = status::success();
    auto sector_lane = output.id;
    result.attach(output_carrier_block->connect(output.cluster.id, 3, sector_lane));
    result.attach(input_carrier_block->connect(3, input.cluster.id, sector_lane));
    auto stack_block = find_stack_t_block(output_carrier);
    return stack_block->connect(output.cluster.id % 3, input.cluster.id % 3, sector_lane);
  }
 
  return status::failure();
}
 
FLASHMEM int clock_idx(CarrierId carrier) {
  auto cluster_id = carrier.id / 3;
  auto stack_id = carrier.stack.id;
  return 2 * stack_id + (stack_id ^ cluster_id);
}
 
FLASHMEM status Router::route_stack(SignalId output, SignalId input) {
  if (output.id < 16 || 32 <= output.id)
    return status("Stack connection lanes out of range");
 
  if (output.id != input.id)
    return status("Can only connect mRedac's common lanes");
 
  auto output_carrier = output.cluster.carrier;
  auto input_carrier = input.cluster.carrier;
 
  auto carrier_sector_lane = output.id - 8;
  auto output_carrier_block = find_carrier_t_block(output_carrier);
 
  // Same stack connections
  if (output_carrier.is_lhs() == input_carrier.is_lhs())
    return output_carrier_block->connect(output.cluster.id, input.cluster.id, carrier_sector_lane);
 
  auto output_clock_idx = clock_idx(output_carrier);
  auto input_clock_idx = clock_idx(input_carrier);
 
  if (16 <= output.id && output.id < 24) {
    bool cw = (output_clock_idx + 1) % 4 == input_clock_idx;
    if (!cw)
      return status("Routing clockwise loop only on output lanes [16, 23]");
  } else if (24 <= output.id && output.id < 32) {
    bool ccw = output_clock_idx == (input_clock_idx + 1) % 4;
    if (!ccw)
      return status("Routing counter clockwise loop only on output lanes [24, 31]");
  }
 
  auto input_carrier_block = find_carrier_t_block(input_carrier);
 
  status result = status::success();
  result.attach(output_carrier_block->connect(output.cluster.id, 3, carrier_sector_lane));
  result.attach(input_carrier_block->connect(3, input.cluster.id, carrier_sector_lane));
 
  auto output_stack_block = find_stack_t_block(output_carrier);
  auto input_stack_block = find_stack_t_block(input_carrier);
  result.attach(output_stack_block->connect(output.cluster.id, 3, carrier_sector_lane));
  result.attach(input_stack_block->connect(3, input.cluster.id, carrier_sector_lane));
  return result;
}
 
FLASHMEM status Router::route(SignalId output, SignalId input) {
  assert(input.id < 32 && output.id < 32);
 
  auto output_node = output.cluster;
  auto input_node = input.cluster;
  assert(output_node.id < 4 && input_node.id < 4);
 
  auto output_carrier = output_node.carrier;
  auto input_carrier = input_node.carrier;
  assert(output_carrier.id < 6 && input_carrier.id < 6);
 
  auto output_stack = output_carrier.stack;
  auto input_stack = input_carrier.stack;
  assert(output_stack.id < 2 && input_stack.id < 2);
 
  if (output_stack != input_stack || output_carrier.is_lhs() != input_carrier.is_lhs())
    return route_stack(output, input);
 
  return route_carrier(output, input);
}