redac.cpp

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// Copyright (c) 2024 anabrid GmbH
// Contact: https://www.anabrid.com/licensing/
//
// SPDX-License-Identifier: MIT OR GPL-2.0-or-later
 
#include "teensy/redac.h"
 
platform::REDAC *platform::REDAC::from_entity_classifier(entities::EntityClassifier classifier,
                                                         __attribute__((__unused__)) const bus::addr_t block_address) {
  if (!classifier or classifier.type != static_cast<uint8_t>(TYPES::mREDAC))
    return nullptr;
 
  if (classifier.version < entities::Version(1))
    return nullptr;
  if (classifier.version < entities::Version(1, 1)) {
    auto *new_carrier = new REDAC(new REDAC_HAL_V_1_0_X);
    new_carrier->classifier = classifier;
    return new_carrier;
  }
  if (classifier.version < entities::Version(1, 2)) {
    auto *new_carrier = new REDAC_V_1_1_X(new REDAC_HAL_V_1_1_X);
    new_carrier->classifier = classifier;
    return new_carrier;
  }
  return nullptr;
}
 
const SPISettings platform::REDAC_HAL_V_1_0_X::BP_REDAC_ID_SPI_SETTINGS{4'000'000, LSBFIRST,
                                                                        SPI_MODE2 /* Chip expects MODE0, CLK is inverted on the way */};
 
const SPISettings platform::REDAC_HAL_V_1_0_X::F_ADC_SWITCHER_PRG_SPI_SETTINGS{
    4'000'000, MSBFIRST, SPI_MODE2 /* chip expects SPI MODE0, but CLK is inverted on the way */};
 
platform::REDAC_HAL_V_1_0_X::REDAC_HAL_V_1_0_X()
    : REDAC_HAL_Parent(bus::CARRIER_BADDR, 15),
 
      bp_redac_id(bus::address_from_tuple(bus::BACKPLANE_BADDR, BP_REDAC_ID_FADDR), 3, BP_REDAC_ID_SPI_SETTINGS),
 
      f_set_standby(bus::address_from_tuple(bus::CARRIER_BADDR, STANDBY_SET_FADDR)),
      f_unset_standby(bus::address_from_tuple(bus::CARRIER_BADDR, STANDBY_UNSET_FADDR)),
      f_adc0_switcher_prg(bus::idx_to_addr(0, bus::REDAC_ADC_PSEUDO_BLOCK_IDX, ADC_PRG_FADDR), 15, F_ADC_SWITCHER_PRG_SPI_SETTINGS),
      f_adc0_switcher_reset(bus::idx_to_addr(0, bus::REDAC_ADC_PSEUDO_BLOCK_IDX, ADC_RESET_FADDR)),
      f_adc0_switcher_sync(bus::idx_to_addr(0, bus::REDAC_ADC_PSEUDO_BLOCK_IDX, ADC_STROBE_FADDR)),
      f_adc1_switcher_prg(bus::idx_to_addr(1, bus::REDAC_ADC_PSEUDO_BLOCK_IDX, ADC_PRG_FADDR), 15, F_ADC_SWITCHER_PRG_SPI_SETTINGS),
      f_adc1_switcher_reset(bus::idx_to_addr(1, bus::REDAC_ADC_PSEUDO_BLOCK_IDX, ADC_RESET_FADDR)),
      f_adc1_switcher_sync(bus::idx_to_addr(1, bus::REDAC_ADC_PSEUDO_BLOCK_IDX, ADC_STROBE_FADDR)),
      f_adc2_switcher_prg(bus::idx_to_addr(2, bus::REDAC_ADC_PSEUDO_BLOCK_IDX, ADC_PRG_FADDR), 15, F_ADC_SWITCHER_PRG_SPI_SETTINGS),
      f_adc2_switcher_reset(bus::idx_to_addr(2, bus::REDAC_ADC_PSEUDO_BLOCK_IDX, ADC_RESET_FADDR)),
      f_adc2_switcher_sync(bus::idx_to_addr(2, bus::REDAC_ADC_PSEUDO_BLOCK_IDX, ADC_STROBE_FADDR)) {}
 
uint16_t platform::REDAC_HAL_V_1_0_X::read_backplane_and_slot_id() const { return bp_redac_id.transfer16(0); }
 
bool platform::REDAC_HAL_V_1_0_X::write_adc_bus_mux(const std::array<int8_t, 8> &channels) {
  // Reset previous connections
  // It's easier to do a full reset then to remember all previous connections
  reset_adc_bus_mux();
  delayNanoseconds(420);
 
  // Write cluster 0 data to chip
  for (uint8_t output_idx = 0; output_idx < channels.size(); output_idx++) {
    if (channels[output_idx] >= 0 && channels[output_idx] < 16) {
      auto cmd = f_adc0_switcher_prg.chip_cmd_word(channels[output_idx], output_idx);
 
      if (!f_adc0_switcher_prg.transfer8(cmd))
        return false;
 
      f_adc0_switcher_sync.trigger();
    }
  }
 
  // Write cluster 1 data to chip
  for (uint8_t output_idx = 0; output_idx < channels.size(); output_idx++) {
    if (channels[output_idx] >= 16 && channels[output_idx] < 32) {
      auto cmd = f_adc1_switcher_prg.chip_cmd_word(channels[output_idx] - 16, output_idx);
 
      if (!f_adc1_switcher_prg.transfer8(cmd))
        return false;
 
      f_adc1_switcher_sync.trigger();
    }
  }
 
  // Write cluster 2 data to chip
  for (uint8_t output_idx = 0; output_idx < channels.size(); output_idx++) {
    if (channels[output_idx] >= 32 && channels[output_idx] < 48) {
      auto cmd = f_adc2_switcher_prg.chip_cmd_word(channels[output_idx] - 32, output_idx);
 
      if (!f_adc2_switcher_prg.transfer8(cmd))
        return false;
 
      f_adc2_switcher_sync.trigger();
    }
  }
 
  return true;
}
 
void platform::REDAC_HAL_V_1_0_X::reset_adc_bus_mux() {
  f_adc0_switcher_reset.trigger();
  f_adc1_switcher_reset.trigger();
  f_adc2_switcher_reset.trigger();
}
 
void platform::REDAC_HAL_V_1_0_X::set_standby(bool enabled) {
  if (enabled)
    f_set_standby.trigger(10000);
  else
    f_unset_standby.trigger(10000);
}
 
platform::REDAC_HAL_V_1_1_X::REDAC_HAL_V_1_1_X()
    : fp_control(bus::address_from_tuple(bus::CARRIER_BADDR, FP_SR), 15, true),
      fp_control_reset(bus::address_from_tuple(bus::CARRIER_BADDR, FP_SR_CLR)),
      fp_control_sync(bus::address_from_tuple(bus::CARRIER_BADDR, FP_SR_STO)) {}
 
bool platform::REDAC_HAL_V_1_1_X::write_fp_control_register(uint16_t state) {
  bool success = fp_control.transfer16(state);
  fp_control_sync.trigger();
  return success;
}
 
status platform::REDAC_V_1_1_X::write_to_hardware() {
  auto stat = REDAC::write_to_hardware();
  stat.attach(status(hardware->write_fp_control_register(fp_control_sr_state)));
  return stat;
}
 
platform::REDAC_V_1_1_X::REDAC_V_1_1_X(REDAC_HAL_V_1_1_X *hardware) : REDAC(hardware), fp_control_sr_state(0), hardware(hardware) {}
 
bool platform::REDAC_V_1_1_X::set_io_mode(uint8_t io_number, FrontPanelIOMode mode) {
  if (mode == FrontPanelIOMode::DIGITAL_IN && io_number != 0)
    return false;
 
  if (mode == FrontPanelIOMode::DIGITAL_OUT && io_number == 0)
    return false;
 
  fp_control_sr_state &= ~(0b10001 << (3 - io_number));
  fp_control_sr_state |= mode << (3 - io_number);
 
  return true;
}
 
platform::REDAC_V_1_1_X::FrontPanelIOMode platform::REDAC_V_1_1_X::get_io_mode(uint8_t io_number) const {
  return static_cast<FrontPanelIOMode>(fp_control_sr_state & (0b10001 << (3 - io_number)) >> (3 - io_number));
}
 
bool platform::REDAC_V_1_1_X::set_DIO_direction(uint8_t dio_number, bool input_from_ctrl_block) {
  uint8_t bit_number = 0;
  if (dio_number == 12)
    bit_number = 8;
  else if (dio_number == 13)
    bit_number = 9;
  else if (dio_number == 28)
    bit_number = 10;
  else if (dio_number == 7)
    bit_number = 11;
  else
    return false;
 
  fp_control_sr_state &= ~(1 << bit_number);
  fp_control_sr_state |= input_from_ctrl_block << bit_number;
 
  return true;
}
 
bool platform::REDAC_V_1_1_X::get_DIO_direction(uint8_t dio_number) const {
  if (dio_number == 12)
    return fp_control_sr_state & (1 << 8);
  if (dio_number == 13)
    return fp_control_sr_state & (1 << 9);
  if (dio_number == 28)
    return fp_control_sr_state & (1 << 10);
  if (dio_number == 7)
    return fp_control_sr_state & (1 << 11);
  return false;
}