mblock_mdr.cpp

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// Copyright (c) 2024 anabrid GmbH
// Contact: https://www.anabrid.com/licensing/
// SPDX-License-Identifier: MIT OR GPL-2.0-or-later
#include <algorithm>
#include <bitset>
 
#include "carrier/carrier.h"
#include "carrier/cluster.h"
 
#include "block/mblock_mdr.h"
#include <block/teensy/mblock_mdr.h>
 
#include "block/mul_calibration.h"
 
using namespace blocks;
 
extern int abs_clamp(float in, int min, int max);
 
blocks::MMDRBlock *blocks::MMDRBlock::from_entity_classifier(entities::EntityClassifier classifier,
                                                                      const bus::addr_t block_address) {
  if (!classifier or classifier.class_enum != CLASS_ or classifier.type != static_cast<uint8_t>(TYPE))
    return nullptr;
 
  // Currently, there are no different variants
  if (classifier.variant != entities::EntityClassifier::DEFAULT_)
    return nullptr;
 
  SLOT slot = block_address % 8 == 4 ? SLOT::M0 : SLOT::M1;
  // Return default implementation
  if (classifier.version < entities::Version(1))
    return nullptr;
  if (classifier.version < entities::Version(1, 1)) {
    auto *new_block = new MMDRBlock(slot, new MMDRBlockHAL_V_1_0_X(block_address));
    new_block->classifier = classifier;
    return new_block;
  }
  return nullptr;
}
 
UnitResult blocks::MMDRBlock::calibrate(platform::Cluster *cluster, carrier::Carrier *carrier) {
  LOG(ANABRID_DEBUG_CALIBRATION, __PRETTY_FUNCTION__);
  TRY(calibrate_mul(carrier, cluster, this, calibration));
  return UnitResult::ok();
}
 
UnitResult blocks::MMDRBlockHAL::init() { return MBlockHAL::init(); }
 
MMDRBlockHAL_V_1_0_X::MMDRBlockHAL_V_1_0_X(bus::addr_t block_address)
    : MMDRBlockHAL_Parent(block_address, 0xff),
      f_overload_flags(bus::replace_function_idx(block_address, 2), 0xff),
      f_overload_flags_reset(bus::replace_function_idx(block_address, 3)),
      f_calibration_dac_0(bus::address_from_tuple(block_address, 4), 0xff, 2.0f),
      f_calibration_dac_1(bus::address_from_tuple(block_address, 5), 0xff, 2.0f),
      f_gain(bus::replace_function_idx(block_address, 6), 0xff),
      f_mode_config(bus::address_from_tuple(block_address, 7), 0xff, true),
      f_mode_config_sync(bus::address_from_tuple(block_address, 8)) {}
 
std::bitset<8> MMDRBlockHAL_V_1_0_X::read_overload_flags() { return f_overload_flags.read8(); }
 
void MMDRBlockHAL_V_1_0_X::reset_overload_flags() { f_overload_flags_reset.trigger(); }
 
bool MMDRBlockHAL_V_1_0_X::write_modes(MMDRBlock::CellMode m0, MMDRBlock::CellMode m1, MMDRBlock::CellMode m2,
                                       MMDRBlock::CellMode m3) {
  // Output of SR is
  // Last bit shifted in > [4bit Cell 3][4 bit Cell 2][4 bit Cell 1][4 bit Cell 0] < First bit shifted in
  // Data is transfered MSBFIRST, so should look like
  // MSB > [4bit Cell 0][Cell 1][Cell 2][Cell 3] < LSB
  uint16_t data = (static_cast<uint16_t>(m0) << 12) | (static_cast<uint16_t>(m1) << 8) |
                  (static_cast<uint16_t>(m2) << 4) | (static_cast<uint16_t>(m3) << 0);
  if (!f_mode_config.transfer16(data))
    return false;
  f_mode_config_sync.trigger();
 
  return true;
}
 
bool MMDRBlockHAL_V_1_0_X::write_calibration_input_offsets(uint8_t idx, uint16_t offset_x,
                                                                    uint16_t offset_y) {
  return f_calibration_dac_0.set_channel_raw(idx * 2, offset_x) and
         f_calibration_dac_0.set_channel_raw(idx * 2 + 1, offset_y);
}
 
bool MMDRBlockHAL_V_1_0_X::write_calibration_output_offset(uint8_t idx, uint16_t offset_z) {
  return f_calibration_dac_1.set_channel_raw(idx, offset_z);
}
 
bool MMDRBlockHAL_V_1_0_X::write_calibration_gain(uint8_t idx, uint8_t gain) {
  if (idx == 0)
    return f_gain.write_channel_raw(2, gain);
  else if (idx == 1)
    return f_gain.write_channel_raw(0, gain);
  else if (idx == 2)
    return f_gain.write_channel_raw(1, gain);
  if (idx == 3)
    return f_gain.write_channel_raw(3, gain);
  return false;
}