50#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U)
51#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)
52#define DCP_HASH_BLOCK_SIZE 128
53#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U)
54#define DCP_KEY_INDEX_MASK (0x30U)
55#define DCP_KEY_INDEX_SHIFT (4U)
56#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)
244#define DCP ((DCP_Type *)0x402FC000)
247 for (
unsigned int i = 0; i < src_len; i++) {
248 dest[i] =
src[src_len - 1 - i];
259 statReg =
DCP->CH0STAT;
260 semaReg =
DCP->CH0SEMA;
264 statReg =
DCP->CH1STAT;
265 semaReg =
DCP->CH1SEMA;
269 statReg =
DCP->CH2STAT;
270 semaReg =
DCP->CH2SEMA;
274 statReg =
DCP->CH3STAT;
275 semaReg =
DCP->CH3SEMA;
290 volatile uint32_t *dcpStatClrPtr = &
DCP->STAT + 2u;
291 *dcpStatClrPtr = 0xFFu;
298 chStatClrPtr = &
DCP->CH0STAT + 2u;
299 *chStatClrPtr = 0xFFu;
302 chStatClrPtr = &
DCP->CH1STAT + 2u;
303 *chStatClrPtr = 0xFFu;
306 chStatClrPtr = &
DCP->CH2STAT + 2u;
307 *chStatClrPtr = 0xFFu;
310 chStatClrPtr = &
DCP->CH3STAT + 2u;
311 *chStatClrPtr = 0xFFu;
343 cmdptr = &
DCP->CH0CMDPTR;
344 chsema = &
DCP->CH0SEMA;
348 cmdptr = &
DCP->CH1CMDPTR;
349 chsema = &
DCP->CH1SEMA;
353 cmdptr = &
DCP->CH2CMDPTR;
354 chsema = &
DCP->CH2SEMA;
358 cmdptr = &
DCP->CH3CMDPTR;
359 chsema = &
DCP->CH3SEMA;
366 if (cmdptr && chsema) {
421 ctxInternal->
ctrl0 = 0;
426 size_t messageSize) {
428 if (ctxInternal->
blksz > 0) {
430 memcpy(&ctxInternal->
blk.
b[ctxInternal->
blksz], message, toCopy);
432 messageSize -= toCopy;
439 uint32_t fullBlocksSize = ((messageSize >> 6) << 6);
440 if (fullBlocksSize > 0) {
442 message += fullBlocksSize;
443 messageSize -= fullBlocksSize;
447 memcpy(&ctxInternal->
blk.
b[0], message, messageSize);
448 ctxInternal->
blksz = messageSize;
454 ctxInternal->
algo = algo;
455 ctxInternal->
blksz = 0u;
456 for (
unsigned int i = 0; i <
sizeof(ctxInternal->
blk.
w) /
sizeof(ctxInternal->
blk.
w[0]); i++) {
457 ctxInternal->
blk.
w[i] = 0u;
461 ctxInternal->
handle = handle;
472 if ((ctxInternal->
blksz + inputSize) <= blockSize) {
473 memcpy((&ctxInternal->
blk.
b[0]) + ctxInternal->
blksz, input, inputSize);
474 ctxInternal->
blksz += inputSize;
478 if (!isUpdateState) {
493 size_t algOutSize = 0;
508 switch (ctxInternal->
algo) {
521 algOutSize = outSize;
536 CCM_CCGR0 |= CCM_CCGR0_DCP(CCM_CCGR_ON);
538 DCP->CTRL = 0xF0800000u;
539 DCP->CTRL = 0x30800000u;
545 DCP->CTRL = 0x00C00000;
552 for (i = 0; i < n; i++) {
553 Serial.printf(
"%02x", h[i]);
563 uint8_t
msg[16 * 1024],
hash[32];
564 static const uint8_t message[] =
"hello";
580 Serial.printf(
"SHA256 %d bytes %d us %.3f MBs\n",
sizeof(
msg), t, (
float)
sizeof(
msg) / t);
587 uint8_t
msg[16 * 1024],
hash[4];
588 static const uint8_t message[] =
"abcdbcdecdefdefgefghfghighijhijk";
589 static const unsigned char crc32[] = {0x7f, 0x04, 0x6a, 0xdd};
598 Serial.printf(
"memcmp %d\n", memcmp(
hash, crc32, 4));
606 Serial.printf(
"CRC32 %d bytes %d us %.3f MBs\n",
sizeof(
msg), t, (
float)
sizeof(
msg) / t);
#define DCP_CH0STAT_ERROR_CODE_MASK
#define DCP_HASH_BLOCK_SIZE
#define DCP_CH0SEMA_VALUE_MASK
enum utils::_dcp_key_slot dcp_key_slot_t
static void dcp_reverse_and_copy(uint8_t *src, uint8_t *dest, size_t src_len)
uint32_t DCP_WaitForChannelComplete(dcp_handle_t *handle)
@ kStatus_InvalidArgument
enum utils::_dcp_swap dcp_swap_t
struct utils::_dcp_handle dcp_handle_t
void prhash(unsigned char *h, int n)
_dcp_work_packet_bit_definitions
@ kDCP_CONTROL0_ENABLE_HASH
@ kDCP_CONTROL1_HASH_SELECT_CRC32
@ kDCP_CONTROL0_HASH_INIT
@ kDCP_CONTROL1_HASH_SELECT_SHA1
@ kDCP_CONTROL0_DECR_SEMAPHOR
@ kDCP_CONTROL1_HASH_SELECT_SHA256
@ kDCP_CONTROL0_HASH_TERM
@ kDCP_ch1Enable
DCP channel 1 enable.
@ kDCP_ch2Enable
DCP channel 2 enable.
@ kDCP_chDisable
DCP channel disable.
@ kDCP_ch0Enable
DCP channel 0 enable.
@ kDCP_chEnableAll
DCP channel enable all.
@ kDCP_ch3Enable
DCP channel 3 enable.
@ kDCP_StateHashUpdate
Update state.
@ kDCP_StateHashInit
Init state.
struct utils::_dcp_hash_ctx_internal dcp_hash_ctx_internal_t
@ kDCP_KeySlot3
DCP key slot 3.
@ kDCP_KeySlot2
DCP key slot 2.
@ kDCP_PayloadKey
DCP payload key.
@ kDCP_KeySlot0
DCP key slot 0.
@ kDCP_OtpUniqueKey
DCP unique OTP key.
@ kDCP_KeySlot1
DCP key slot 1.
@ kDCP_OtpKey
DCP OTP key.
struct utils::_dcp_work_packet dcp_work_packet_t
static uint32_t dcp_schedule_work(dcp_handle_t *handle, dcp_work_packet_t *dcpPacket)
static void dcp_clear_channel_status(uint32_t mask)
enum utils::_dcp_hash_algo_t dcp_hash_algo_t
void hash_sha1(const uint8_t *msg, size_t msg_len, uint8_t *out_hash)
void dcp_hash_update(dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *msg, size_t size)
void hash_sha256(const uint8_t *msg, size_t msg_len, uint8_t *out_hash)
Computes the SHA256 sum of an arbitrary message (large memory segment).
enum utils::_dcp_channel dcp_channel_t
static void dcp_clear_status()
void hash(const uint8_t *msg, size_t msg_len, uint8_t *out_hash, dcp_hash_algo_t algo)
@ kDCP_Channel3
DCP channel 3.
@ kDCP_Channel2
DCP channel 2.
@ kDCP_Channel1
DCP channel 1.
@ kDCP_Channel0
DCP channel 0.
void DCP_HASH_Update(dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize)
void DCP_HASH_Init(dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo)
static uint32_t dcp_get_channel_status(dcp_channel_t channel)
union utils::_dcp_hash_block dcp_hash_block_t
void dcp_hash_process_message_data(dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *message, size_t messageSize)
static uint32_t dcp_hash_update_non_blocking(dcp_hash_ctx_internal_t *ctxInternal, dcp_work_packet_t *dcpPacket, const uint8_t *msg, size_t size)
struct utils::_dcp_hash_ctx_t dcp_hash_ctx_t
enum utils::_dcp_hash_algo_state dcp_hash_algo_state_t
enum utils::_dcp_ch_enable _dcp_ch_enable_t
void DCP_HASH_Finish(dcp_hash_ctx_t *ctx, uint8_t *output)
DCP - Register Layout Typedef.
volatile uint32_t KEYDATA
DCP key data, offset: 0x70.
volatile uint32_t CH2STAT
DCP channel 2 status register, offset: 0x1A0.
volatile uint32_t CH3OPTS
DCP channel 3 options register, offset: 0x1F0.
volatile uint32_t CH1CMDPTR
DCP channel 1 command pointer address register, offset: 0x140.
volatile uint32_t CTRL
DCP control register 0, offset: 0x0.
volatile uint32_t PACKET3
DCP work packet 3 status register, offset: 0xB0.
volatile uint32_t CH1SEMA
DCP channel 1 semaphore register, offset: 0x150.
volatile uint32_t PACKET0
DCP work packet 0 status register, offset: 0x80.
volatile uint32_t PACKET4
DCP work packet 4 status register, offset: 0xC0.
volatile uint32_t CH0SEMA
DCP channel 0 semaphore register, offset: 0x110.
volatile uint32_t CAPABILITY1
DCP capability 1 register, offset: 0x40.
volatile uint32_t CH2OPTS
DCP channel 2 options register, offset: 0x1B0.
volatile uint32_t CH3SEMA
DCP channel 3 semaphore register, offset: 0x1D0.
volatile uint32_t CH1STAT
DCP channel 1 status register, offset: 0x160.
volatile uint32_t CH0OPTS
DCP channel 0 options register, offset: 0x130.
volatile uint32_t CONTEXT
DCP context buffer pointer, offset: 0x50.
volatile uint32_t CH3CMDPTR
DCP channel 3 command pointer address register, offset: 0x1C0.
volatile uint32_t KEY
DCP key index, offset: 0x60.
volatile uint32_t CH2CMDPTR
DCP channel 2 command pointer address register, offset: 0x180.
volatile uint32_t VERSION
DCP version register, offset: 0x430.
volatile uint32_t PACKET5
DCP work packet 5 status register, offset: 0xD0.
volatile uint32_t CH0STAT
DCP channel 0 status register, offset: 0x120.
volatile uint32_t PACKET6
DCP work packet 6 status register, offset: 0xE0.
volatile uint32_t CAPABILITY0
DCP capability 0 register, offset: 0x30.
volatile uint32_t CH1OPTS
DCP channel 1 options register, offset: 0x170.
volatile uint32_t CH0CMDPTR
DCP channel 0 command pointer address register, offset: 0x100.
volatile uint32_t CH2SEMA
DCP channel 2 semaphore register, offset: 0x190.
volatile uint32_t PACKET2
DCP work packet 2 status register, offset: 0xA0.
volatile uint32_t PAGETABLE
DCP page table register, offset: 0x420.
volatile uint32_t DBGDATA
DCP debug data register, offset: 0x410.
volatile uint32_t CH3STAT
DCP channel 3 status register, offset: 0x1E0.
volatile uint32_t DBGSELECT
DCP debug select register, offset: 0x400.
volatile uint32_t STAT
DCP status register, offset: 0x10.
volatile uint32_t PACKET1
DCP work packet 1 status register, offset: 0x90.
volatile uint32_t CHANNELCTRL
DCP channel control register, offset: 0x20.
uint32_t swapConfig
For configuration of key, input, output byte/word swap options.
dcp_key_slot_t keySlot
For operations with key (such as AES encryption/decryption), specify DCP key slot.
dcp_channel_t channel
Specify DCP channel.
dcp_hash_block_t blk
memory buffer.
dcp_hash_algo_t algo
selected algorithm from the set of supported algorithms
dcp_hash_algo_state_t state
finite machine state of the hash software process
uint32_t fullMessageSize
track message size
uint32_t ctrl0
HASH_INIT and HASH_TERM flags.
size_t blksz
number of valid bytes in memory buffer
uint32_t runningHash[9]
running hash.
uint32_t destinationBufferAddress
uint32_t sourceBufferAddress
uint32_t w[128/4]
array of 32-bit words