REDAC HybridController
Firmware for LUCIDAC/REDAC Teensy
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dcp.cpp
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1
36// T4 DCP AES SHA CRC32
37// tests on channel 0 non-blocking no context switching
38
39#include <Arduino.h> // noInterrupts(), interrupts()
40
41#include "utils/dcp.h"
42
43using namespace std;
44
45namespace utils {
46
47// InputOutput or just Input
48#define __IO volatile
49#define __I volatile
50#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U)
51#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)
52#define DCP_HASH_BLOCK_SIZE 128
53#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U)
54#define DCP_KEY_INDEX_MASK (0x30U)
55#define DCP_KEY_INDEX_SHIFT (4U)
56#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)
57
67
76
77typedef enum _dcp_channel {
78 kDCP_Channel0 = (1u << 16),
79 kDCP_Channel1 = (1u << 17),
80 kDCP_Channel2 = (1u << 18),
81 kDCP_Channel3 = (1u << 19),
83
93
103
109
115
117 kDCP_CONTROL0_DECR_SEMAPHOR = 1u << 1, /* DECR_SEMAPHOR */
118 kDCP_CONTROL0_ENABLE_HASH = 1u << 6, /* ENABLE_HASH */
119 kDCP_CONTROL0_HASH_INIT = 1u << 12, /* HASH_INIT */
120 kDCP_CONTROL0_HASH_TERM = 1u << 13, /* HASH_TERM */
124};
125
129
134
139
148
159
170
172typedef struct {
174 uint8_t RESERVED_0[12];
176 uint8_t RESERVED_1[12];
178 uint8_t RESERVED_2[12];
180 uint8_t RESERVED_3[12];
182 uint8_t RESERVED_4[12];
184 uint8_t RESERVED_5[12];
186 uint8_t RESERVED_6[12];
188 uint8_t RESERVED_7[12];
190 uint8_t RESERVED_8[12];
192 uint8_t RESERVED_9[12];
194 uint8_t RESERVED_10[12];
196 uint8_t RESERVED_11[12];
198 uint8_t RESERVED_12[12];
200 uint8_t RESERVED_13[12];
202 uint8_t RESERVED_14[28];
204 uint8_t RESERVED_15[12];
206 uint8_t RESERVED_16[12];
208 uint8_t RESERVED_17[12];
210 uint8_t RESERVED_18[12];
212 uint8_t RESERVED_19[12];
214 uint8_t RESERVED_20[12];
216 uint8_t RESERVED_21[12];
218 uint8_t RESERVED_22[12];
220 uint8_t RESERVED_23[12];
222 uint8_t RESERVED_24[12];
224 uint8_t RESERVED_25[12];
226 uint8_t RESERVED_26[12];
228 uint8_t RESERVED_27[12];
230 uint8_t RESERVED_28[12];
232 uint8_t RESERVED_29[12];
234 uint8_t RESERVED_30[524];
236 uint8_t RESERVED_31[12];
238 uint8_t RESERVED_32[12];
240 uint8_t RESERVED_33[12];
242} DCP_Type;
243
244#define DCP ((DCP_Type *)0x402FC000)
245
246FLASHMEM static void dcp_reverse_and_copy(uint8_t *src, uint8_t *dest, size_t src_len) {
247 for (unsigned int i = 0; i < src_len; i++) {
248 dest[i] = src[src_len - 1 - i];
249 }
250}
251
253 uint32_t statReg = 0;
254 uint32_t semaReg = 0;
256
257 switch (channel) {
258 case kDCP_Channel0:
259 statReg = DCP->CH0STAT;
260 semaReg = DCP->CH0SEMA;
261 break;
262
263 case kDCP_Channel1:
264 statReg = DCP->CH1STAT;
265 semaReg = DCP->CH1SEMA;
266 break;
267
268 case kDCP_Channel2:
269 statReg = DCP->CH2STAT;
270 semaReg = DCP->CH2SEMA;
271 break;
272
273 case kDCP_Channel3:
274 statReg = DCP->CH3STAT;
275 semaReg = DCP->CH3SEMA;
276 break;
277
278 default:
279 break;
280 }
281
282 if (!((semaReg & DCP_CH0SEMA_VALUE_MASK) || (statReg & DCP_CH0STAT_ERROR_CODE_MASK))) {
284 }
285
286 return status;
287}
288
289FLASHMEM static void dcp_clear_status() {
290 volatile uint32_t *dcpStatClrPtr = &DCP->STAT + 2u;
291 *dcpStatClrPtr = 0xFFu;
292}
293
294FLASHMEM static void dcp_clear_channel_status(uint32_t mask) {
295 volatile uint32_t *chStatClrPtr;
296
297 if (mask & kDCP_Channel0) {
298 chStatClrPtr = &DCP->CH0STAT + 2u;
299 *chStatClrPtr = 0xFFu;
300 }
301 if (mask & kDCP_Channel1) {
302 chStatClrPtr = &DCP->CH1STAT + 2u;
303 *chStatClrPtr = 0xFFu;
304 }
305 if (mask & kDCP_Channel2) {
306 chStatClrPtr = &DCP->CH2STAT + 2u;
307 *chStatClrPtr = 0xFFu;
308 }
309 if (mask & kDCP_Channel3) {
310 chStatClrPtr = &DCP->CH3STAT + 2u;
311 *chStatClrPtr = 0xFFu;
312 }
313}
314
316 /* wait if our channel is still active */
317 while ((DCP->STAT & (uint32_t)handle->channel) == handle->channel) {
318 }
319
323 return kStatus_Fail;
324 }
325
326 return kStatus_Success;
327}
328
329FLASHMEM static uint32_t dcp_schedule_work(dcp_handle_t *handle, dcp_work_packet_t *dcpPacket) {
331
332 /* check if our channel is active */
333 if ((DCP->STAT & (uint32_t)handle->channel) != handle->channel) {
334 noInterrupts();
335
336 /* re-check if our channel is still available */
337 if ((DCP->STAT & (uint32_t)handle->channel) == 0) {
338 volatile uint32_t *cmdptr = NULL;
339 volatile uint32_t *chsema = NULL;
340
341 switch (handle->channel) {
342 case kDCP_Channel0:
343 cmdptr = &DCP->CH0CMDPTR;
344 chsema = &DCP->CH0SEMA;
345 break;
346
347 case kDCP_Channel1:
348 cmdptr = &DCP->CH1CMDPTR;
349 chsema = &DCP->CH1SEMA;
350 break;
351
352 case kDCP_Channel2:
353 cmdptr = &DCP->CH2CMDPTR;
354 chsema = &DCP->CH2SEMA;
355 break;
356
357 case kDCP_Channel3:
358 cmdptr = &DCP->CH3CMDPTR;
359 chsema = &DCP->CH3SEMA;
360 break;
361
362 default:
363 break;
364 }
365
366 if (cmdptr && chsema) {
367 /* set out packet to DCP CMDPTR */
368 *cmdptr = (uint32_t)dcpPacket;
369
370 /* set the channel semaphore */
371 *chsema = 1u;
372 }
374 }
375
376 else {
378 }
379 interrupts();
380 }
381
382 else {
383 return kStatus_DCP_Again;
384 }
385
386 return status;
387}
388
390 dcp_work_packet_t *dcpPacket, const uint8_t *msg,
391 size_t size) {
392 dcpPacket->control0 = ctxInternal->ctrl0 | (ctxInternal->handle->swapConfig & 0xFC0000u) |
394 if (ctxInternal->algo == kDCP_Sha256) {
396 } else if (ctxInternal->algo == kDCP_Sha1) {
398 } else if (ctxInternal->algo == kDCP_Crc32) {
400 } else {
401 return 1;
402 }
403 dcpPacket->sourceBufferAddress = (uint32_t)msg;
404 dcpPacket->destinationBufferAddress = 0;
405 dcpPacket->bufferSize = size;
406 dcpPacket->payloadPointer = (uint32_t)ctxInternal->runningHash;
407
408 return dcp_schedule_work(ctxInternal->handle, dcpPacket);
409}
410
411void dcp_hash_update(dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *msg, size_t size) {
412 uint32_t completionStatus;
413 dcp_work_packet_t dcpWork = {0};
414
415 do {
416 completionStatus = dcp_hash_update_non_blocking(ctxInternal, &dcpWork, msg, size);
417 } while (completionStatus == kStatus_DCP_Again);
418
419 completionStatus = DCP_WaitForChannelComplete(ctxInternal->handle);
420
421 ctxInternal->ctrl0 = 0; /* clear kDCP_CONTROL0_HASH_INIT and kDCP_CONTROL0_HASH_TERM flags */
422 return; // (completionStatus);
423}
424
425FLASHMEM void dcp_hash_process_message_data(dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *message,
426 size_t messageSize) {
427 /* if there is partially filled internal buffer, fill it to full block */
428 if (ctxInternal->blksz > 0) {
429 size_t toCopy = DCP_HASH_BLOCK_SIZE - ctxInternal->blksz;
430 memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy);
431 message += toCopy;
432 messageSize -= toCopy;
433
434 /* process full internal block */
435 dcp_hash_update(ctxInternal, &ctxInternal->blk.b[0], DCP_HASH_BLOCK_SIZE);
436 }
437
438 /* process all full blocks in message[] */
439 uint32_t fullBlocksSize = ((messageSize >> 6) << 6); /* (X / 64) * 64 */
440 if (fullBlocksSize > 0) {
441 dcp_hash_update(ctxInternal, message, fullBlocksSize);
442 message += fullBlocksSize;
443 messageSize -= fullBlocksSize;
444 }
445
446 /* copy last incomplete message bytes into internal block */
447 memcpy(&ctxInternal->blk.b[0], message, messageSize);
448 ctxInternal->blksz = messageSize;
449}
450
451FLASHMEM void DCP_HASH_Init(dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo) {
452 dcp_hash_ctx_internal_t *ctxInternal;
453 ctxInternal = (dcp_hash_ctx_internal_t *)ctx;
454 ctxInternal->algo = algo;
455 ctxInternal->blksz = 0u;
456 for (unsigned int i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) {
457 ctxInternal->blk.w[i] = 0u; // bug was 0
458 }
459 ctxInternal->state = kDCP_StateHashInit;
460 ctxInternal->fullMessageSize = 0;
461 ctxInternal->handle = handle;
462}
463
464FLASHMEM void DCP_HASH_Update(dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize) {
465 bool isUpdateState;
466 dcp_hash_ctx_internal_t *ctxInternal;
467 size_t blockSize = DCP_HASH_BLOCK_SIZE;
468
469 ctxInternal = (dcp_hash_ctx_internal_t *)ctx;
470 ctxInternal->fullMessageSize += inputSize;
471 /* if we are still less than DCP_HASH_BLOCK_SIZE bytes, keep only in context */
472 if ((ctxInternal->blksz + inputSize) <= blockSize) {
473 memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize);
474 ctxInternal->blksz += inputSize;
475 return;
476 } else {
477 isUpdateState = ctxInternal->state == kDCP_StateHashUpdate;
478 if (!isUpdateState) {
479 /* start NEW hash */
480 ctxInternal->ctrl0 = kDCP_CONTROL0_HASH_INIT;
481 ctxInternal->state = kDCP_StateHashUpdate;
482 } else {
483 // dcp_hash_restore_running_hash(ctxInternal); // context switch
484 }
485 }
486
487 /* process input data */
488 dcp_hash_process_message_data(ctxInternal, input, inputSize);
489 // dcp_hash_save_running_hash(ctxInternal); // context
490}
491
492FLASHMEM void DCP_HASH_Finish(dcp_hash_ctx_t *ctx, uint8_t *output) {
493 size_t algOutSize = 0;
494 dcp_hash_ctx_internal_t *ctxInternal;
495
496 ctxInternal = (dcp_hash_ctx_internal_t *)ctx;
497
498 if (ctxInternal->state == kDCP_StateHashInit) {
499 ctxInternal->ctrl0 = kDCP_CONTROL0_HASH_INIT; // dcp_hash_engine_init( ctxInternal);
500
501 } else {
502 // dcp_hash_restore_running_hash(ctxInternal); // context
503 }
504
505 size_t outSize = 0u;
506
507 /* compute algorithm output length */
508 switch (ctxInternal->algo) {
509 case kDCP_Sha256:
510 outSize = kDCP_OutLenSha256;
511 break;
512 case kDCP_Sha1:
513 outSize = kDCP_OutLenSha1;
514 break;
515 case kDCP_Crc32:
516 outSize = kDCP_OutLenCrc32;
517 break;
518 default:
519 break;
520 }
521 algOutSize = outSize;
522
523 /* flush message last incomplete block, if there is any, and add padding bits */
524 // dcp_hash_finalize( ctxInternal);
525 ctxInternal->ctrl0 |= kDCP_CONTROL0_HASH_TERM;
526 dcp_hash_update(ctxInternal, &ctxInternal->blk.b[0], ctxInternal->blksz);
527
528 /* Reverse and copy result to output[] */
529 dcp_reverse_and_copy((uint8_t *)ctxInternal->runningHash, &output[0], algOutSize);
530
531 memset(ctx, 0, sizeof(dcp_hash_ctx_t));
532}
533
534FLASHMEM void dcp_init() {
535 // volatile uint32_t *p;
536 CCM_CCGR0 |= CCM_CCGR0_DCP(CCM_CCGR_ON); // DCP on
537
538 DCP->CTRL = 0xF0800000u; /* reset value */
539 DCP->CTRL = 0x30800000u; /* default value */
540
542 // clear channel status
544
545 DCP->CTRL = 0x00C00000; // enable caching writes
546 DCP->CHANNELCTRL = kDCP_ch0Enable;
547}
548
549FLASHMEM void prhash(unsigned char *h, int n) {
550 int i;
551
552 for (i = 0; i < n; i++) {
553 Serial.printf("%02x", h[i]);
554 if (i % 4 == 3)
555 Serial.printf(" ");
556 }
557 Serial.printf("\n");
558}
559
560FLASHMEM void demo_sha256() {
561 dcp_handle_t m_handle;
562 dcp_hash_ctx_t hashCtx;
563 uint8_t msg[16 * 1024], hash[32]; // msg is actually big kind-of-random
564 static const uint8_t message[] = "hello"; // hash 2cf24dba ...
565
566 m_handle.channel = kDCP_Channel0;
567 m_handle.keySlot = kDCP_KeySlot0;
568 m_handle.swapConfig = kDCP_NoSwap;
569
570 DCP_HASH_Init(&m_handle, &hashCtx, kDCP_Sha256);
571 DCP_HASH_Update(&hashCtx, message, 5);
572 DCP_HASH_Finish(&hashCtx, hash);
573 prhash(hash, 32);
574
575 uint32_t t = micros();
576 DCP_HASH_Init(&m_handle, &hashCtx, kDCP_Sha256);
577 DCP_HASH_Update(&hashCtx, msg, sizeof(msg));
578 DCP_HASH_Finish(&hashCtx, hash);
579 t = micros() - t;
580 Serial.printf("SHA256 %d bytes %d us %.3f MBs\n", sizeof(msg), t, (float)sizeof(msg) / t);
581 prhash(hash, 32);
582}
583
584FLASHMEM void demo_crc32() {
585 dcp_handle_t m_handle;
586 dcp_hash_ctx_t hashCtx;
587 uint8_t msg[16 * 1024], hash[4];
588 static const uint8_t message[] = "abcdbcdecdefdefgefghfghighijhijk";
589 static const unsigned char crc32[] = {0x7f, 0x04, 0x6a, 0xdd}; // crc
590
591 m_handle.channel = kDCP_Channel0;
592 m_handle.keySlot = kDCP_KeySlot0;
593 m_handle.swapConfig = kDCP_NoSwap;
594
595 DCP_HASH_Init(&m_handle, &hashCtx, kDCP_Crc32);
596 DCP_HASH_Update(&hashCtx, message, sizeof(message) - 1);
597 DCP_HASH_Finish(&hashCtx, hash);
598 Serial.printf("memcmp %d\n", memcmp(hash, crc32, 4));
599 prhash(hash, 4);
600
601 uint32_t t = micros();
602 DCP_HASH_Init(&m_handle, &hashCtx, kDCP_Crc32);
603 DCP_HASH_Update(&hashCtx, msg, sizeof(msg));
604 DCP_HASH_Finish(&hashCtx, hash);
605 t = micros() - t;
606 Serial.printf("CRC32 %d bytes %d us %.3f MBs\n", sizeof(msg), t, (float)sizeof(msg) / t);
607 prhash(hash, 4);
608}
609
610FLASHMEM void hash(const uint8_t *msg, size_t msg_len, uint8_t *out_hash, dcp_hash_algo_t algo) {
611 dcp_init();
612
613 dcp_handle_t m_handle;
614 dcp_hash_ctx_t hashCtx;
615
616 m_handle.channel = kDCP_Channel0;
617 m_handle.keySlot = kDCP_KeySlot0;
618 m_handle.swapConfig = kDCP_NoSwap;
619
620 DCP_HASH_Init(&m_handle, &hashCtx, algo);
621 DCP_HASH_Update(&hashCtx, msg, msg_len);
622 DCP_HASH_Finish(&hashCtx, out_hash);
623}
624
630FLASHMEM void hash_sha256(const uint8_t *msg, size_t msg_len, uint8_t *out_hash) {
631 hash(msg, msg_len, out_hash, kDCP_Sha256);
632}
633
634FLASHMEM void hash_sha1(const uint8_t *msg, size_t msg_len, uint8_t *out_hash) {
635 hash(msg, msg_len, out_hash, kDCP_Sha1);
636}
637
638} // namespace utils
utils::status status
Definition daq.h:21
uint32_t
Definition flasher.cpp:195
uint32_t src
Definition flasher.cpp:63
uint32_t uint32_t size
Definition flasher.cpp:63
#define DCP_CH0STAT_ERROR_CODE_MASK
Definition dcp.cpp:51
#define DCP_HASH_BLOCK_SIZE
Definition dcp.cpp:52
#define DCP_CH0SEMA_VALUE_MASK
Definition dcp.cpp:50
#define DCP
Definition dcp.cpp:244
#define __IO
Definition dcp.cpp:48
#define __I
Definition dcp.cpp:49
FLASHMEM void DCP_HASH_Update(dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize)
Definition dcp.cpp:464
FLASHMEM void dcp_init()
Definition dcp.cpp:534
static FLASHMEM uint32_t dcp_get_channel_status(dcp_channel_t channel)
Definition dcp.cpp:252
enum utils::_dcp_key_slot dcp_key_slot_t
uint32_t DCP_WaitForChannelComplete(dcp_handle_t *handle)
Definition dcp.cpp:315
_generic_status
Definition dcp.cpp:58
@ kStatus_Fail
Definition dcp.cpp:60
@ kStatus_OutOfRange
Definition dcp.cpp:62
@ kStatus_Success
Definition dcp.cpp:59
@ kStatus_ReadOnly
Definition dcp.cpp:61
@ kStatus_Timeout
Definition dcp.cpp:64
@ kStatus_InvalidArgument
Definition dcp.cpp:63
@ kStatus_DCP_Again
Definition dcp.cpp:65
enum utils::_dcp_swap dcp_swap_t
FLASHMEM void prhash(unsigned char *h, int n)
Definition dcp.cpp:549
FLASHMEM void DCP_HASH_Finish(dcp_hash_ctx_t *ctx, uint8_t *output)
Definition dcp.cpp:492
struct utils::_dcp_handle dcp_handle_t
_dcp_work_packet_bit_definitions
Definition dcp.cpp:116
@ kDCP_CONTROL0_ENABLE_HASH
Definition dcp.cpp:118
@ kDCP_CONTROL1_HASH_SELECT_CRC32
Definition dcp.cpp:123
@ kDCP_CONTROL0_HASH_INIT
Definition dcp.cpp:119
@ kDCP_CONTROL1_HASH_SELECT_SHA1
Definition dcp.cpp:122
@ kDCP_CONTROL0_DECR_SEMAPHOR
Definition dcp.cpp:117
@ kDCP_CONTROL1_HASH_SELECT_SHA256
Definition dcp.cpp:121
@ kDCP_CONTROL0_HASH_TERM
Definition dcp.cpp:120
static FLASHMEM uint32_t dcp_hash_update_non_blocking(dcp_hash_ctx_internal_t *ctxInternal, dcp_work_packet_t *dcpPacket, const uint8_t *msg, size_t size)
Definition dcp.cpp:389
FLASHMEM void hash(const uint8_t *msg, size_t msg_len, uint8_t *out_hash, dcp_hash_algo_t algo)
Definition dcp.cpp:610
_dcp_ch_enable
Definition dcp.cpp:68
@ kDCP_ch1Enable
DCP channel 1 enable.
Definition dcp.cpp:71
@ kDCP_ch2Enable
DCP channel 2 enable.
Definition dcp.cpp:72
@ kDCP_chDisable
DCP channel disable.
Definition dcp.cpp:69
@ kDCP_ch0Enable
DCP channel 0 enable.
Definition dcp.cpp:70
@ kDCP_chEnableAll
DCP channel enable all.
Definition dcp.cpp:74
@ kDCP_ch3Enable
DCP channel 3 enable.
Definition dcp.cpp:73
static FLASHMEM uint32_t dcp_schedule_work(dcp_handle_t *handle, dcp_work_packet_t *dcpPacket)
Definition dcp.cpp:329
_dcp_hash_algo_state
Definition dcp.cpp:135
@ kDCP_StateHashUpdate
Update state.
Definition dcp.cpp:137
@ kDCP_StateHashInit
Init state.
Definition dcp.cpp:136
static FLASHMEM void dcp_reverse_and_copy(uint8_t *src, uint8_t *dest, size_t src_len)
Definition dcp.cpp:246
struct utils::_dcp_hash_ctx_internal dcp_hash_ctx_internal_t
_dcp_key_slot
Definition dcp.cpp:84
@ kDCP_KeySlot3
DCP key slot 3.
Definition dcp.cpp:88
@ kDCP_KeySlot2
DCP key slot 2.
Definition dcp.cpp:87
@ kDCP_PayloadKey
DCP payload key.
Definition dcp.cpp:91
@ kDCP_KeySlot0
DCP key slot 0.
Definition dcp.cpp:85
@ kDCP_OtpUniqueKey
DCP unique OTP key.
Definition dcp.cpp:90
@ kDCP_KeySlot1
DCP key slot 1.
Definition dcp.cpp:86
@ kDCP_OtpKey
DCP OTP key.
Definition dcp.cpp:89
struct utils::_dcp_work_packet dcp_work_packet_t
enum utils::_dcp_hash_algo_t dcp_hash_algo_t
FLASHMEM void hash_sha1(const uint8_t *msg, size_t msg_len, uint8_t *out_hash)
Definition dcp.cpp:634
FLASHMEM void DCP_HASH_Init(dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo)
Definition dcp.cpp:451
void dcp_hash_update(dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *msg, size_t size)
Definition dcp.cpp:411
static FLASHMEM void dcp_clear_status()
Definition dcp.cpp:289
FLASHMEM void hash_sha256(const uint8_t *msg, size_t msg_len, uint8_t *out_hash)
Computes the SHA256 sum of an arbitrary message (large memory segment).
Definition dcp.cpp:630
enum utils::_dcp_channel dcp_channel_t
_dcp_swap
Definition dcp.cpp:94
@ kDCP_NoSwap
Definition dcp.cpp:95
@ kDCP_InputWordSwap
Definition dcp.cpp:99
@ kDCP_KeyByteSwap
Definition dcp.cpp:96
@ kDCP_InputByteSwap
Definition dcp.cpp:98
@ kDCP_OutputByteSwap
Definition dcp.cpp:100
@ kDCP_KeyWordSwap
Definition dcp.cpp:97
@ kDCP_OutputWordSwap
Definition dcp.cpp:101
FLASHMEM void demo_sha256()
Definition dcp.cpp:560
_dcp_channel
Definition dcp.cpp:77
@ kDCP_Channel3
DCP channel 3.
Definition dcp.cpp:81
@ kDCP_Channel2
DCP channel 2.
Definition dcp.cpp:80
@ kDCP_Channel1
DCP channel 1.
Definition dcp.cpp:79
@ kDCP_Channel0
DCP channel 0.
Definition dcp.cpp:78
FLASHMEM void demo_crc32()
Definition dcp.cpp:584
static FLASHMEM void dcp_clear_channel_status(uint32_t mask)
Definition dcp.cpp:294
union utils::_dcp_hash_block dcp_hash_block_t
FLASHMEM void dcp_hash_process_message_data(dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *message, size_t messageSize)
Definition dcp.cpp:425
struct utils::_dcp_hash_ctx_t dcp_hash_ctx_t
_dcp_hash_algo_t
Definition dcp.cpp:104
@ kDCP_Sha1
SHA_1.
Definition dcp.cpp:105
@ kDCP_Crc32
CRC_32.
Definition dcp.cpp:107
@ kDCP_Sha256
SHA_256.
Definition dcp.cpp:106
enum utils::_dcp_hash_algo_state dcp_hash_algo_state_t
_dcp_hash_digest_len
Definition dcp.cpp:110
@ kDCP_OutLenSha1
Definition dcp.cpp:111
@ kDCP_OutLenSha256
Definition dcp.cpp:112
@ kDCP_OutLenCrc32
Definition dcp.cpp:113
enum utils::_dcp_ch_enable _dcp_ch_enable_t
DCP - Register Layout Typedef.
Definition dcp.cpp:172
volatile uint32_t KEYDATA
DCP key data, offset: 0x70.
Definition dcp.cpp:187
volatile uint32_t CH2STAT
DCP channel 2 status register, offset: 0x1A0.
Definition dcp.cpp:223
volatile uint32_t CH3OPTS
DCP channel 3 options register, offset: 0x1F0.
Definition dcp.cpp:233
volatile uint32_t CH1CMDPTR
DCP channel 1 command pointer address register, offset: 0x140.
Definition dcp.cpp:211
volatile uint32_t CTRL
DCP control register 0, offset: 0x0.
Definition dcp.cpp:173
volatile uint32_t PACKET3
DCP work packet 3 status register, offset: 0xB0.
Definition dcp.cpp:195
volatile uint32_t CH1SEMA
DCP channel 1 semaphore register, offset: 0x150.
Definition dcp.cpp:213
volatile uint32_t PACKET0
DCP work packet 0 status register, offset: 0x80.
Definition dcp.cpp:189
volatile uint32_t PACKET4
DCP work packet 4 status register, offset: 0xC0.
Definition dcp.cpp:197
volatile uint32_t CH0SEMA
DCP channel 0 semaphore register, offset: 0x110.
Definition dcp.cpp:205
volatile uint32_t CAPABILITY1
DCP capability 1 register, offset: 0x40.
Definition dcp.cpp:181
volatile uint32_t CH2OPTS
DCP channel 2 options register, offset: 0x1B0.
Definition dcp.cpp:225
volatile uint32_t CH3SEMA
DCP channel 3 semaphore register, offset: 0x1D0.
Definition dcp.cpp:229
volatile uint32_t CH1STAT
DCP channel 1 status register, offset: 0x160.
Definition dcp.cpp:215
volatile uint32_t CH0OPTS
DCP channel 0 options register, offset: 0x130.
Definition dcp.cpp:209
volatile uint32_t CONTEXT
DCP context buffer pointer, offset: 0x50.
Definition dcp.cpp:183
volatile uint32_t CH3CMDPTR
DCP channel 3 command pointer address register, offset: 0x1C0.
Definition dcp.cpp:227
volatile uint32_t KEY
DCP key index, offset: 0x60.
Definition dcp.cpp:185
volatile uint32_t CH2CMDPTR
DCP channel 2 command pointer address register, offset: 0x180.
Definition dcp.cpp:219
volatile uint32_t VERSION
DCP version register, offset: 0x430.
Definition dcp.cpp:241
volatile uint32_t PACKET5
DCP work packet 5 status register, offset: 0xD0.
Definition dcp.cpp:199
volatile uint32_t CH0STAT
DCP channel 0 status register, offset: 0x120.
Definition dcp.cpp:207
volatile uint32_t PACKET6
DCP work packet 6 status register, offset: 0xE0.
Definition dcp.cpp:201
volatile uint32_t CAPABILITY0
DCP capability 0 register, offset: 0x30.
Definition dcp.cpp:179
volatile uint32_t CH1OPTS
DCP channel 1 options register, offset: 0x170.
Definition dcp.cpp:217
volatile uint32_t CH0CMDPTR
DCP channel 0 command pointer address register, offset: 0x100.
Definition dcp.cpp:203
volatile uint32_t CH2SEMA
DCP channel 2 semaphore register, offset: 0x190.
Definition dcp.cpp:221
volatile uint32_t PACKET2
DCP work packet 2 status register, offset: 0xA0.
Definition dcp.cpp:193
volatile uint32_t PAGETABLE
DCP page table register, offset: 0x420.
Definition dcp.cpp:239
volatile uint32_t DBGDATA
DCP debug data register, offset: 0x410.
Definition dcp.cpp:237
volatile uint32_t CH3STAT
DCP channel 3 status register, offset: 0x1E0.
Definition dcp.cpp:231
volatile uint32_t DBGSELECT
DCP debug select register, offset: 0x400.
Definition dcp.cpp:235
volatile uint32_t STAT
DCP status register, offset: 0x10.
Definition dcp.cpp:175
volatile uint32_t PACKET1
DCP work packet 1 status register, offset: 0x90.
Definition dcp.cpp:191
volatile uint32_t CHANNELCTRL
DCP channel control register, offset: 0x20.
Definition dcp.cpp:177
uint32_t swapConfig
For configuration of key, input, output byte/word swap options.
Definition dcp.cpp:144
dcp_key_slot_t keySlot
For operations with key (such as AES encryption/decryption), specify DCP key slot.
Definition dcp.cpp:143
uint32_t iv[4]
Definition dcp.cpp:146
dcp_channel_t channel
Specify DCP channel.
Definition dcp.cpp:141
uint32_t keyWord[4]
Definition dcp.cpp:145
dcp_hash_block_t blk
memory buffer.
Definition dcp.cpp:150
dcp_hash_algo_t algo
selected algorithm from the set of supported algorithms
Definition dcp.cpp:152
dcp_hash_algo_state_t state
finite machine state of the hash software process
Definition dcp.cpp:153
uint32_t fullMessageSize
track message size
Definition dcp.cpp:154
dcp_handle_t * handle
Definition dcp.cpp:157
uint32_t ctrl0
HASH_INIT and HASH_TERM flags.
Definition dcp.cpp:155
size_t blksz
number of valid bytes in memory buffer
Definition dcp.cpp:151
uint32_t runningHash[9]
running hash.
Definition dcp.cpp:156
uint32_t x[58]
Definition dcp.cpp:127
uint32_t destinationBufferAddress
Definition dcp.cpp:165
uint32_t payloadPointer
Definition dcp.cpp:167
uint32_t sourceBufferAddress
Definition dcp.cpp:164
uint32_t nextCmdAddress
Definition dcp.cpp:161
uint8_t b[128]
byte array
Definition dcp.cpp:132
uint32_t w[128/4]
array of 32-bit words
Definition dcp.cpp:131