tblock.cpp

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#include "teensy/tblock.h"
 
#include <bitset>
 
using namespace blocks;
 
const SPISettings TBlockHAL_V_1_0_X::F_CONNECTION_SPI_SETTINGS{
    4'000'000, MSBFIRST, SPI_MODE2 /* Chip expects MODE0, CLK is inverted on the way, but MOSI is not, thus CLK must be shifted */};
 
TBlockHAL_V_1_0_X::TBlockHAL_V_1_0_X(bus::addr_t block_address)
    : TBlockHAL_Parent(block_address, 7), f_set_mux_disable{bus::replace_function_idx(block_address, 5)},
      f_reset_mux_disable{bus::replace_function_idx(block_address, 6)}, f_reset_connections{bus::replace_function_idx(block_address, 4)},
      f_connections{bus::replace_function_idx(block_address, 2), 7, F_CONNECTION_SPI_SETTINGS}, f_connections_sync{
                                                                                                    bus::replace_function_idx(block_address, 3)} {}
 
void TBlockHAL_V_1_0_X::set_mux_disable() { f_set_mux_disable.trigger(); }
 
void TBlockHAL_V_1_0_X::reset_mux_disable() { f_reset_mux_disable.trigger(); }
 
bool TBlockHAL_V_1_0_X::write_muxes(std::array<uint8_t, NUM_SWITCHES> muxes) {
  // Order of muxes in function argument is sources for output [bpl_ch0, cl0_ch0, cl1_ch0, cl2_ch0, bpl_ch1,
  // ... cl2_ch23]
  std::array<uint8_t, NUM_REGISTERS> data{};
  for (auto idx = 0u; idx < data.size(); idx++) {
    // Fill up MOSI buffer in reverse because MSBFirst flag doesnt mirror the byte order but only the bytes
    // alone
    data[data.size() - 1 - idx] = (muxes[idx * 4 + 3] << 6) | (muxes[idx * 4 + 2] << 4) | (muxes[idx * 4 + 1] << 2) | muxes[idx * 4 + 0];
  }
 
  auto success = f_connections.transfer(data.data(), nullptr, data.size());
  f_connections_sync.trigger();
  return success;
}
 
bool TBlockHAL_V_1_0_X::reset_muxes() {
  f_reset_connections.trigger();
#ifdef ANABRID_PEDANTIC
  std::array<uint8_t, 24> data{0};
  f_connections.transfer(data.data(), data.data(), data.size());
  return std::all_of(data.begin(), data.end(), [](auto value) { return value == 0; });
#else
  return true;
#endif
}
 
TBlock *TBlock::from_entity_classifier(entities::EntityClassifier classifier, bus::addr_t block_address) {
  if (!classifier or classifier.class_enum != CLASS_ or classifier.type != TYPE)
    return nullptr;
 
  if (classifier.version < entities::Version(1, 0, 2))
    // Version 1.0.1 was manufactured without any muxers on them :)
    return nullptr;
  if (classifier.version < entities::Version(1, 1)) {
    auto *new_tblock = new TBlock(new TBlockHAL_V_1_0_X(block_address));
    new_tblock->classifier = classifier;
    return new_tblock;
  }
  return nullptr;
}
 
TBlockBackplane *TBlockBackplane::from_entity_classifier(entities::EntityClassifier classifier, bus::addr_t block_address) {
  if (!classifier or classifier.class_enum != CLASS_ or classifier.type != TYPE)
    return nullptr;
 
  if (classifier.version < entities::Version(1, 0, 0))
    return nullptr;
  if (classifier.version < entities::Version(1, 1)) {
    auto *new_tblock = new TBlockBackplane(new TBlockBackplaneHAL_V_1_0_X(block_address));
    new_tblock->classifier = classifier;
    return new_tblock;
  }
  return nullptr;
}
 
// Backplane T Block
const SPISettings TBlockBackplaneHAL_V_1_0_X::F_CONNECTION_SPI_SETTINGS{
    4'000'000, MSBFIRST, SPI_MODE2 /* Chip expects MODE0, CLK is inverted on the way, but MOSI is not, thus CLK must be shifted */};
 
TBlockBackplaneHAL_V_1_0_X::TBlockBackplaneHAL_V_1_0_X(bus::addr_t block_address)
    : TBlockBackplaneHAL_Parent(block_address, 0xff), f_set_mux_disable{bus::replace_function_idx(block_address, 5)},
      f_reset_mux_disable{bus::replace_function_idx(block_address, 6)}, f_connections{bus::replace_function_idx(block_address, 2), 0xff,
                                                                                      F_CONNECTION_SPI_SETTINGS},
      f_reset_connections{bus::replace_function_idx(block_address, 4)}, f_connections_sync{bus::replace_function_idx(block_address, 3)} {}
 
template <size_t NumBits>
constexpr auto bitset2array(const std::bitset<NumBits>& bits)
    -> std::array<uint8_t, (NumBits + 7) / 8>
{
  constexpr size_t NumBytes = (NumBits + 7) / 8;
  std::array<uint8_t, NumBytes> result{};
 
  for (size_t i = 0; i < NumBits; ++i) {
    if (bits[i]) {
      result[i / 8] |= (1 << (7 - i % 8));
    }
  }
 
  return result;
}
 
bool TBlockBackplaneHAL_V_1_0_X::write_muxes(std::array<uint8_t, NUM_SWITCHES> muxes) {
  // Order of mux data is completly crazy, as we have 3 bits per mux. So each byte holds partial data for three muxes
  // Fill up MOSI buffer in reverse because MSBFirst flag doesnt mirror the byte order but only the bytes
  // alone
 
  std::bitset<NUM_SWITCHES * 3> out_data;
 
  for (uint16_t idx = 0; idx < muxes.size(); idx++) {
    uint16_t rev_idx = muxes.size() - idx - 1;
    uint16_t slot = rev_idx * 3;
    out_data[slot + 0] = muxes[idx] & (1 << 2);
    out_data[slot + 1] = muxes[idx] & (1 << 1);
    out_data[slot + 2] = muxes[idx] & (1 << 0);
  }
 
  auto array = bitset2array(out_data);
  auto success = f_connections.transfer(array.data(), nullptr, NUM_REGISTERS);
  f_connections_sync.trigger();
  return success;
}
 
bool TBlockBackplaneHAL_V_1_0_X::reset_muxes() {
  f_reset_connections.trigger();
#ifdef ANABRID_PEDANTIC
  std::array<uint8_t, NUM_REGISTERS> data{0};
  f_connections.transfer(data.data(), data.data(), data.size());
  return std::all_of(data.begin(), data.end(), [](auto value) { return value == 0; });
#else
  return true;
#endif
}
 
void TBlockBackplaneHAL_V_1_0_X::set_mux_disable() { f_set_mux_disable.trigger(); }
 
void TBlockBackplaneHAL_V_1_0_X::reset_mux_disable() { f_reset_mux_disable.trigger(); }