eeprom.cpp

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/* Teensyduino Core Library
 * http://www.pjrc.com/teensy/
 * Copyright (c) 2019 PJRC.COM, LLC.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * 1. The above copyright notice and this permission notice shall be 
 * included in all copies or substantial portions of the Software.
 *
 * 2. If the Software is incorporated into a build system that allows 
 * selection among a list of target devices, then similar target
 * devices manufactured by PJRC.COM must be included in the list of
 * target devices and selectable in the same manner.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
 
// To configure the EEPROM size, edit E2END in avr/eeprom.h.
//
// Generally you should avoid editing this code, unless you really
// know what you're doing.
 
#include "imxrt.h"
#include <avr/eeprom.h>
#include <string.h>
#include <avr/pgmspace.h>
 
#include "debug/printf.h"
 
#if defined(ARDUINO_TEENSY40)
#define FLASH_BASEADDR 0x601F0000
#define FLASH_SECTORS  15
#elif defined(ARDUINO_TEENSY41)
#define FLASH_BASEADDR 0x607C0000
#define FLASH_SECTORS  63
#elif defined(ARDUINO_TEENSY_MICROMOD)
#define FLASH_BASEADDR 0x60FC0000
#define FLASH_SECTORS  63
#endif
 
 
#if E2END > (255*FLASH_SECTORS-1)
#error "E2END is set larger than the maximum possible EEPROM size"
#endif
 
// Conversation about how this code works & what the upper limits are
// https://forum.pjrc.com/threads/57377?p=214566&viewfull=1#post214566
 
// To be called from LittleFS_Program, any other use at your own risk!
void flash_write(void *addr, const void *data, uint32_t len);
void flash_erase_sector(void *addr);
void flash_erase_32K_block(void *addr);
void flash_erase_64K_block(void *addr);
 
#define LUT0(opcode, pads, operand) (FLEXSPI_LUT_INSTRUCTION((opcode), (pads), (operand)))
#define LUT1(opcode, pads, operand) (FLEXSPI_LUT_INSTRUCTION((opcode), (pads), (operand)) << 16)
#define CMD_SDR         FLEXSPI_LUT_OPCODE_CMD_SDR
#define ADDR_SDR        FLEXSPI_LUT_OPCODE_RADDR_SDR
#define READ_SDR        FLEXSPI_LUT_OPCODE_READ_SDR
#define WRITE_SDR       FLEXSPI_LUT_OPCODE_WRITE_SDR
#define PINS1           FLEXSPI_LUT_NUM_PADS_1
#define PINS4           FLEXSPI_LUT_NUM_PADS_4
 
FASTRUN
static void flash_wait()
{
    FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x05) | LUT1(READ_SDR, PINS1, 1); // 05 = read status
    FLEXSPI_LUT61 = 0;
    uint8_t status;
    do {
        FLEXSPI_IPRXFCR = FLEXSPI_IPRXFCR_CLRIPRXF; // clear rx fifo
        FLEXSPI_IPCR0 = 0;
        FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15) | FLEXSPI_IPCR1_IDATSZ(1);
        FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG;
        while (!(FLEXSPI_INTR & FLEXSPI_INTR_IPCMDDONE)) {;}
        FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE;
        asm("":::"memory");
        status = *(uint8_t *)&FLEXSPI_RFDR0;
    } while (status & 1);
    FLEXSPI_MCR0 |= FLEXSPI_MCR0_SWRESET; // purge stale data from FlexSPI's AHB FIFO
    while (FLEXSPI_MCR0 & FLEXSPI_MCR0_SWRESET) ; // wait
}
 
// write bytes into flash memory (which is already erased to 0xFF)
FASTRUN
void flash_write(void *addr, const void *data, uint32_t len)
{
    FLEXSPI_LUTKEY = FLEXSPI_LUTKEY_VALUE;
    FLEXSPI_LUTCR = FLEXSPI_LUTCR_UNLOCK;
    FLEXSPI_IPCR0 = 0;
    FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x06); // 06 = write enable
    FLEXSPI_LUT61 = 0;
    FLEXSPI_LUT62 = 0;
    FLEXSPI_LUT63 = 0;
    FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15);
    FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG;
    arm_dcache_delete(addr, len); // purge old data from ARM's cache
    while (!(FLEXSPI_INTR & FLEXSPI_INTR_IPCMDDONE)) ; // wait
    FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE;
    FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x32) | LUT1(ADDR_SDR, PINS1, 24); // 32 = quad write
    FLEXSPI_LUT61 = LUT0(WRITE_SDR, PINS4, 1);
    FLEXSPI_IPTXFCR = FLEXSPI_IPTXFCR_CLRIPTXF; // clear tx fifo
    FLEXSPI_IPCR0 = (uint32_t)addr & 0x00FFFFFF;
    FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15) | FLEXSPI_IPCR1_IDATSZ(len);
    FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG;
    const uint8_t *src = (const uint8_t *)data;
    uint32_t n;
    while (!((n = FLEXSPI_INTR) & FLEXSPI_INTR_IPCMDDONE)) {
        if (n & FLEXSPI_INTR_IPTXWE) {
            uint32_t wrlen = len;
            if (wrlen > 8) wrlen = 8;
            if (wrlen > 0) {
                memcpy((void *)&FLEXSPI_TFDR0, src, wrlen);
                src += wrlen;
                len -= wrlen;
            }
            FLEXSPI_INTR = FLEXSPI_INTR_IPTXWE;
        }
    }
    FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE | FLEXSPI_INTR_IPTXWE;
    flash_wait();
}
 
// erase a 4K sector
FASTRUN
void flash_erase_sector(void *addr)
{
    FLEXSPI_LUTKEY = FLEXSPI_LUTKEY_VALUE;
    FLEXSPI_LUTCR = FLEXSPI_LUTCR_UNLOCK;
    FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x06); // 06 = write enable
    FLEXSPI_LUT61 = 0;
    FLEXSPI_LUT62 = 0;
    FLEXSPI_LUT63 = 0;
    FLEXSPI_IPCR0 = 0;
    FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15);
    FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG;
    arm_dcache_delete((void *)((uint32_t)addr & 0xFFFFF000), 4096); // purge data from cache
    while (!(FLEXSPI_INTR & FLEXSPI_INTR_IPCMDDONE)) ; // wait
    FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE;
    FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x20) | LUT1(ADDR_SDR, PINS1, 24); // 20 = sector erase
    FLEXSPI_IPCR0 = (uint32_t)addr & 0x00FFF000;
    FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15);
    FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG;
    while (!(FLEXSPI_INTR & FLEXSPI_INTR_IPCMDDONE)) ; // wait
    FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE;
    flash_wait();
}
 
FASTRUN
void flash_erase_32K_block(void *addr)
{
    FLEXSPI_LUTKEY = FLEXSPI_LUTKEY_VALUE;
    FLEXSPI_LUTCR = FLEXSPI_LUTCR_UNLOCK;
    FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x06); // 06 = write enable
    FLEXSPI_LUT61 = 0;
    FLEXSPI_LUT62 = 0;
    FLEXSPI_LUT63 = 0;
    FLEXSPI_IPCR0 = 0;
    FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15);
    FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG;
    arm_dcache_delete((void *)((uint32_t)addr & 0xFFFF8000), 32768); // purge data from cache
    while (!(FLEXSPI_INTR & FLEXSPI_INTR_IPCMDDONE)) ; // wait
    FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE;
    FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x52) | LUT1(ADDR_SDR, PINS1, 24); // 52 = 32K erase
    FLEXSPI_IPCR0 = (uint32_t)addr & 0x00FF8000;
    FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15);
    FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG;
    while (!(FLEXSPI_INTR & FLEXSPI_INTR_IPCMDDONE)) ; // wait
    FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE;
    flash_wait();
}
 
FASTRUN
void flash_erase_64K_block(void *addr)
{
    FLEXSPI_LUTKEY = FLEXSPI_LUTKEY_VALUE;
    FLEXSPI_LUTCR = FLEXSPI_LUTCR_UNLOCK;
    FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0x06); // 06 = write enable
    FLEXSPI_LUT61 = 0;
    FLEXSPI_LUT62 = 0;
    FLEXSPI_LUT63 = 0;
    FLEXSPI_IPCR0 = 0;
    FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15);
    FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG;
    arm_dcache_delete((void *)((uint32_t)addr & 0xFFFF0000), 65536); // purge data from cache
    while (!(FLEXSPI_INTR & FLEXSPI_INTR_IPCMDDONE)) ; // wait
    FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE;
    FLEXSPI_LUT60 = LUT0(CMD_SDR, PINS1, 0xD8) | LUT1(ADDR_SDR, PINS1, 24); // D8 = 64K erase
    FLEXSPI_IPCR0 = (uint32_t)addr & 0x00FF0000;
    FLEXSPI_IPCR1 = FLEXSPI_IPCR1_ISEQID(15);
    FLEXSPI_IPCMD = FLEXSPI_IPCMD_TRG;
    while (!(FLEXSPI_INTR & FLEXSPI_INTR_IPCMDDONE)) ; // wait
    FLEXSPI_INTR = FLEXSPI_INTR_IPCMDDONE;
    flash_wait();
}