REDAC HybridController
Firmware for LUCIDAC/REDAC Teensy
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dcp.cpp
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1
36// T4 DCP AES SHA CRC32
37// tests on channel 0 non-blocking no context switching
38
39#include <Arduino.h> // noInterrupts(), interrupts()
40
41#ifdef ARDUINO
42
43#include "utils/dcp.h"
44
45using namespace std;
46
47namespace utils {
48
49// InputOutput or just Input
50#define __IO volatile
51#define __I volatile
52#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U)
53#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)
54#define DCP_HASH_BLOCK_SIZE 128
55#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U)
56#define DCP_KEY_INDEX_MASK (0x30U)
57#define DCP_KEY_INDEX_SHIFT (4U)
58#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)
59
69
78
79typedef enum _dcp_channel {
80 kDCP_Channel0 = (1u << 16),
81 kDCP_Channel1 = (1u << 17),
82 kDCP_Channel2 = (1u << 18),
83 kDCP_Channel3 = (1u << 19),
85
95
105
111
117
119 kDCP_CONTROL0_DECR_SEMAPHOR = 1u << 1, /* DECR_SEMAPHOR */
120 kDCP_CONTROL0_ENABLE_HASH = 1u << 6, /* ENABLE_HASH */
121 kDCP_CONTROL0_HASH_INIT = 1u << 12, /* HASH_INIT */
122 kDCP_CONTROL0_HASH_TERM = 1u << 13, /* HASH_TERM */
126};
127
131
136
141
150
161
172
174typedef struct {
176 uint8_t RESERVED_0[12];
178 uint8_t RESERVED_1[12];
180 uint8_t RESERVED_2[12];
182 uint8_t RESERVED_3[12];
184 uint8_t RESERVED_4[12];
186 uint8_t RESERVED_5[12];
188 uint8_t RESERVED_6[12];
190 uint8_t RESERVED_7[12];
192 uint8_t RESERVED_8[12];
194 uint8_t RESERVED_9[12];
196 uint8_t RESERVED_10[12];
198 uint8_t RESERVED_11[12];
200 uint8_t RESERVED_12[12];
202 uint8_t RESERVED_13[12];
204 uint8_t RESERVED_14[28];
206 uint8_t RESERVED_15[12];
208 uint8_t RESERVED_16[12];
210 uint8_t RESERVED_17[12];
212 uint8_t RESERVED_18[12];
214 uint8_t RESERVED_19[12];
216 uint8_t RESERVED_20[12];
218 uint8_t RESERVED_21[12];
220 uint8_t RESERVED_22[12];
222 uint8_t RESERVED_23[12];
224 uint8_t RESERVED_24[12];
226 uint8_t RESERVED_25[12];
228 uint8_t RESERVED_26[12];
230 uint8_t RESERVED_27[12];
232 uint8_t RESERVED_28[12];
234 uint8_t RESERVED_29[12];
236 uint8_t RESERVED_30[524];
238 uint8_t RESERVED_31[12];
240 uint8_t RESERVED_32[12];
242 uint8_t RESERVED_33[12];
244} DCP_Type;
245
246#define DCP ((DCP_Type *)0x402FC000)
247
248FLASHMEM static void dcp_reverse_and_copy(uint8_t *src, uint8_t *dest, size_t src_len) {
249 for (unsigned int i = 0; i < src_len; i++) {
250 dest[i] = src[src_len - 1 - i];
251 }
252}
253
255 uint32_t statReg = 0;
256 uint32_t semaReg = 0;
258
259 switch (channel) {
260 case kDCP_Channel0:
261 statReg = DCP->CH0STAT;
262 semaReg = DCP->CH0SEMA;
263 break;
264
265 case kDCP_Channel1:
266 statReg = DCP->CH1STAT;
267 semaReg = DCP->CH1SEMA;
268 break;
269
270 case kDCP_Channel2:
271 statReg = DCP->CH2STAT;
272 semaReg = DCP->CH2SEMA;
273 break;
274
275 case kDCP_Channel3:
276 statReg = DCP->CH3STAT;
277 semaReg = DCP->CH3SEMA;
278 break;
279
280 default:
281 break;
282 }
283
284 if (!((semaReg & DCP_CH0SEMA_VALUE_MASK) || (statReg & DCP_CH0STAT_ERROR_CODE_MASK))) {
286 }
287
288 return status;
289}
290
291FLASHMEM static void dcp_clear_status() {
292 volatile uint32_t *dcpStatClrPtr = &DCP->STAT + 2u;
293 *dcpStatClrPtr = 0xFFu;
294}
295
296FLASHMEM static void dcp_clear_channel_status(uint32_t mask) {
297 volatile uint32_t *chStatClrPtr;
298
299 if (mask & kDCP_Channel0) {
300 chStatClrPtr = &DCP->CH0STAT + 2u;
301 *chStatClrPtr = 0xFFu;
302 }
303 if (mask & kDCP_Channel1) {
304 chStatClrPtr = &DCP->CH1STAT + 2u;
305 *chStatClrPtr = 0xFFu;
306 }
307 if (mask & kDCP_Channel2) {
308 chStatClrPtr = &DCP->CH2STAT + 2u;
309 *chStatClrPtr = 0xFFu;
310 }
311 if (mask & kDCP_Channel3) {
312 chStatClrPtr = &DCP->CH3STAT + 2u;
313 *chStatClrPtr = 0xFFu;
314 }
315}
316
318 /* wait if our channel is still active */
319 while ((DCP->STAT & (uint32_t)handle->channel) == handle->channel) {
320 }
321
325 return kStatus_Fail;
326 }
327
328 return kStatus_Success;
329}
330
331FLASHMEM static uint32_t dcp_schedule_work(dcp_handle_t *handle, dcp_work_packet_t *dcpPacket) {
333
334 /* check if our channel is active */
335 if ((DCP->STAT & (uint32_t)handle->channel) != handle->channel) {
336 noInterrupts();
337
338 /* re-check if our channel is still available */
339 if ((DCP->STAT & (uint32_t)handle->channel) == 0) {
340 volatile uint32_t *cmdptr = NULL;
341 volatile uint32_t *chsema = NULL;
342
343 switch (handle->channel) {
344 case kDCP_Channel0:
345 cmdptr = &DCP->CH0CMDPTR;
346 chsema = &DCP->CH0SEMA;
347 break;
348
349 case kDCP_Channel1:
350 cmdptr = &DCP->CH1CMDPTR;
351 chsema = &DCP->CH1SEMA;
352 break;
353
354 case kDCP_Channel2:
355 cmdptr = &DCP->CH2CMDPTR;
356 chsema = &DCP->CH2SEMA;
357 break;
358
359 case kDCP_Channel3:
360 cmdptr = &DCP->CH3CMDPTR;
361 chsema = &DCP->CH3SEMA;
362 break;
363
364 default:
365 break;
366 }
367
368 if (cmdptr && chsema) {
369 /* set out packet to DCP CMDPTR */
370 *cmdptr = (uint32_t)dcpPacket;
371
372 /* set the channel semaphore */
373 *chsema = 1u;
374 }
376 }
377
378 else {
380 }
381 interrupts();
382 }
383
384 else {
385 return kStatus_DCP_Again;
386 }
387
388 return status;
389}
390
392 dcp_work_packet_t *dcpPacket, const uint8_t *msg, size_t size) {
393 dcpPacket->control0 = ctxInternal->ctrl0 | (ctxInternal->handle->swapConfig & 0xFC0000u) |
395 if (ctxInternal->algo == kDCP_Sha256) {
397 } else if (ctxInternal->algo == kDCP_Sha1) {
399 } else if (ctxInternal->algo == kDCP_Crc32) {
401 } else {
402 return 1;
403 }
404 dcpPacket->sourceBufferAddress = (uint32_t)msg;
405 dcpPacket->destinationBufferAddress = 0;
406 dcpPacket->bufferSize = size;
407 dcpPacket->payloadPointer = (uint32_t)ctxInternal->runningHash;
408
409 return dcp_schedule_work(ctxInternal->handle, dcpPacket);
410}
411
412void dcp_hash_update(dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *msg, size_t size) {
413 uint32_t completionStatus;
414 dcp_work_packet_t dcpWork = {0};
415
416 do {
417 completionStatus = dcp_hash_update_non_blocking(ctxInternal, &dcpWork, msg, size);
418 } while (completionStatus == kStatus_DCP_Again);
419
420 completionStatus = DCP_WaitForChannelComplete(ctxInternal->handle);
421
422 ctxInternal->ctrl0 = 0; /* clear kDCP_CONTROL0_HASH_INIT and kDCP_CONTROL0_HASH_TERM flags */
423 return; // (completionStatus);
424}
425
426FLASHMEM void dcp_hash_process_message_data(dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *message,
427 size_t messageSize) {
428 /* if there is partially filled internal buffer, fill it to full block */
429 if (ctxInternal->blksz > 0) {
430 size_t toCopy = DCP_HASH_BLOCK_SIZE - ctxInternal->blksz;
431 memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy);
432 message += toCopy;
433 messageSize -= toCopy;
434
435 /* process full internal block */
436 dcp_hash_update(ctxInternal, &ctxInternal->blk.b[0], DCP_HASH_BLOCK_SIZE);
437 }
438
439 /* process all full blocks in message[] */
440 uint32_t fullBlocksSize = ((messageSize >> 6) << 6); /* (X / 64) * 64 */
441 if (fullBlocksSize > 0) {
442 dcp_hash_update(ctxInternal, message, fullBlocksSize);
443 message += fullBlocksSize;
444 messageSize -= fullBlocksSize;
445 }
446
447 /* copy last incomplete message bytes into internal block */
448 memcpy(&ctxInternal->blk.b[0], message, messageSize);
449 ctxInternal->blksz = messageSize;
450}
451
452FLASHMEM void DCP_HASH_Init(dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo) {
453 dcp_hash_ctx_internal_t *ctxInternal;
454 ctxInternal = (dcp_hash_ctx_internal_t *)ctx;
455 ctxInternal->algo = algo;
456 ctxInternal->blksz = 0u;
457 for (unsigned int i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) {
458 ctxInternal->blk.w[i] = 0u; // bug was 0
459 }
460 ctxInternal->state = kDCP_StateHashInit;
461 ctxInternal->fullMessageSize = 0;
462 ctxInternal->handle = handle;
463}
464
465FLASHMEM void DCP_HASH_Update(dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize) {
466 bool isUpdateState;
467 dcp_hash_ctx_internal_t *ctxInternal;
468 size_t blockSize = DCP_HASH_BLOCK_SIZE;
469
470 ctxInternal = (dcp_hash_ctx_internal_t *)ctx;
471 ctxInternal->fullMessageSize += inputSize;
472 /* if we are still less than DCP_HASH_BLOCK_SIZE bytes, keep only in context */
473 if ((ctxInternal->blksz + inputSize) <= blockSize) {
474 memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize);
475 ctxInternal->blksz += inputSize;
476 return;
477 } else {
478 isUpdateState = ctxInternal->state == kDCP_StateHashUpdate;
479 if (!isUpdateState) {
480 /* start NEW hash */
481 ctxInternal->ctrl0 = kDCP_CONTROL0_HASH_INIT;
482 ctxInternal->state = kDCP_StateHashUpdate;
483 } else {
484 // dcp_hash_restore_running_hash(ctxInternal); // context switch
485 }
486 }
487
488 /* process input data */
489 dcp_hash_process_message_data(ctxInternal, input, inputSize);
490 // dcp_hash_save_running_hash(ctxInternal); // context
491}
492
493FLASHMEM void DCP_HASH_Finish(dcp_hash_ctx_t *ctx, uint8_t *output) {
494 size_t algOutSize = 0;
495 dcp_hash_ctx_internal_t *ctxInternal;
496
497 ctxInternal = (dcp_hash_ctx_internal_t *)ctx;
498
499 if (ctxInternal->state == kDCP_StateHashInit) {
500 ctxInternal->ctrl0 = kDCP_CONTROL0_HASH_INIT; // dcp_hash_engine_init( ctxInternal);
501
502 } else {
503 // dcp_hash_restore_running_hash(ctxInternal); // context
504 }
505
506 size_t outSize = 0u;
507
508 /* compute algorithm output length */
509 switch (ctxInternal->algo) {
510 case kDCP_Sha256:
511 outSize = kDCP_OutLenSha256;
512 break;
513 case kDCP_Sha1:
514 outSize = kDCP_OutLenSha1;
515 break;
516 case kDCP_Crc32:
517 outSize = kDCP_OutLenCrc32;
518 break;
519 default:
520 break;
521 }
522 algOutSize = outSize;
523
524 /* flush message last incomplete block, if there is any, and add padding bits */
525 // dcp_hash_finalize( ctxInternal);
526 ctxInternal->ctrl0 |= kDCP_CONTROL0_HASH_TERM;
527 dcp_hash_update(ctxInternal, &ctxInternal->blk.b[0], ctxInternal->blksz);
528
529 /* Reverse and copy result to output[] */
530 dcp_reverse_and_copy((uint8_t *)ctxInternal->runningHash, &output[0], algOutSize);
531
532 memset(ctx, 0, sizeof(dcp_hash_ctx_t));
533}
534
535FLASHMEM void dcp_init() {
536 // volatile uint32_t *p;
537 CCM_CCGR0 |= CCM_CCGR0_DCP(CCM_CCGR_ON); // DCP on
538
539 DCP->CTRL = 0xF0800000u; /* reset value */
540 DCP->CTRL = 0x30800000u; /* default value */
541
543 // clear channel status
545
546 DCP->CTRL = 0x00C00000; // enable caching writes
547 DCP->CHANNELCTRL = kDCP_ch0Enable;
548}
549
550FLASHMEM void prhash(unsigned char *h, int n) {
551 int i;
552
553 for (i = 0; i < n; i++) {
554 Serial.printf("%02x", h[i]);
555 if (i % 4 == 3)
556 Serial.printf(" ");
557 }
558 Serial.printf("\n");
559}
560
561FLASHMEM void demo_sha256() {
562 dcp_handle_t m_handle;
563 dcp_hash_ctx_t hashCtx;
564 uint8_t msg[16 * 1024], hash[32]; // msg is actually big kind-of-random
565 static const uint8_t message[] = "hello"; // hash 2cf24dba ...
566
567 m_handle.channel = kDCP_Channel0;
568 m_handle.keySlot = kDCP_KeySlot0;
569 m_handle.swapConfig = kDCP_NoSwap;
570
571 DCP_HASH_Init(&m_handle, &hashCtx, kDCP_Sha256);
572 DCP_HASH_Update(&hashCtx, message, 5);
573 DCP_HASH_Finish(&hashCtx, hash);
574 prhash(hash, 32);
575
576 uint32_t t = micros();
577 DCP_HASH_Init(&m_handle, &hashCtx, kDCP_Sha256);
578 DCP_HASH_Update(&hashCtx, msg, sizeof(msg));
579 DCP_HASH_Finish(&hashCtx, hash);
580 t = micros() - t;
581 Serial.printf("SHA256 %d bytes %d us %.3f MBs\n", sizeof(msg), t, (float)sizeof(msg) / t);
582 prhash(hash, 32);
583}
584
585FLASHMEM void demo_crc32() {
586 dcp_handle_t m_handle;
587 dcp_hash_ctx_t hashCtx;
588 uint8_t msg[16 * 1024], hash[4];
589 static const uint8_t message[] = "abcdbcdecdefdefgefghfghighijhijk";
590 static const unsigned char crc32[] = {0x7f, 0x04, 0x6a, 0xdd}; // crc
591
592 m_handle.channel = kDCP_Channel0;
593 m_handle.keySlot = kDCP_KeySlot0;
594 m_handle.swapConfig = kDCP_NoSwap;
595
596 DCP_HASH_Init(&m_handle, &hashCtx, kDCP_Crc32);
597 DCP_HASH_Update(&hashCtx, message, sizeof(message) - 1);
598 DCP_HASH_Finish(&hashCtx, hash);
599 Serial.printf("memcmp %d\n", memcmp(hash, crc32, 4));
600 prhash(hash, 4);
601
602 uint32_t t = micros();
603 DCP_HASH_Init(&m_handle, &hashCtx, kDCP_Crc32);
604 DCP_HASH_Update(&hashCtx, msg, sizeof(msg));
605 DCP_HASH_Finish(&hashCtx, hash);
606 t = micros() - t;
607 Serial.printf("CRC32 %d bytes %d us %.3f MBs\n", sizeof(msg), t, (float)sizeof(msg) / t);
608 prhash(hash, 4);
609}
610
611FLASHMEM void hash(const uint8_t *msg, size_t msg_len, uint8_t *out_hash, dcp_hash_algo_t algo) {
612 dcp_init();
613
614 dcp_handle_t m_handle;
615 dcp_hash_ctx_t hashCtx;
616
617 m_handle.channel = kDCP_Channel0;
618 m_handle.keySlot = kDCP_KeySlot0;
619 m_handle.swapConfig = kDCP_NoSwap;
620
621 DCP_HASH_Init(&m_handle, &hashCtx, algo);
622 DCP_HASH_Update(&hashCtx, msg, msg_len);
623 DCP_HASH_Finish(&hashCtx, out_hash);
624}
625
631FLASHMEM void hash_sha256(const uint8_t *msg, size_t msg_len, uint8_t *out_hash) {
632 hash(msg, msg_len, out_hash, kDCP_Sha256);
633}
634
635FLASHMEM void hash_sha1(const uint8_t *msg, size_t msg_len, uint8_t *out_hash) {
636 hash(msg, msg_len, out_hash, kDCP_Sha1);
637}
638
639} // namespace utils
640
641#endif /* \
642#include <Arduino.h> // noInterrupts(), interrupts() */
A recoverable error, inspired from https://abseil.io/docs/cpp/guides/status and https://github....
Definition error.h:35
utils::status status
Definition daq.h:28
#define DCP_CH0STAT_ERROR_CODE_MASK
Definition dcp.cpp:53
#define DCP_HASH_BLOCK_SIZE
Definition dcp.cpp:54
#define DCP_CH0SEMA_VALUE_MASK
Definition dcp.cpp:52
#define DCP
Definition dcp.cpp:246
#define __IO
Definition dcp.cpp:50
#define __I
Definition dcp.cpp:51
uint32_t
Definition flasher.cpp:195
uint32_t src
Definition flasher.cpp:63
uint32_t uint32_t size
Definition flasher.cpp:63
Definition carrier.h:12
STL namespace.
FLASHMEM void DCP_HASH_Update(dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize)
Definition dcp.cpp:465
FLASHMEM void dcp_init()
Definition dcp.cpp:535
static FLASHMEM uint32_t dcp_get_channel_status(dcp_channel_t channel)
Definition dcp.cpp:254
enum utils::_dcp_key_slot dcp_key_slot_t
uint32_t DCP_WaitForChannelComplete(dcp_handle_t *handle)
Definition dcp.cpp:317
_generic_status
Definition dcp.cpp:60
@ kStatus_Fail
Definition dcp.cpp:62
@ kStatus_OutOfRange
Definition dcp.cpp:64
@ kStatus_Success
Definition dcp.cpp:61
@ kStatus_ReadOnly
Definition dcp.cpp:63
@ kStatus_Timeout
Definition dcp.cpp:66
@ kStatus_InvalidArgument
Definition dcp.cpp:65
@ kStatus_DCP_Again
Definition dcp.cpp:67
enum utils::_dcp_swap dcp_swap_t
FLASHMEM void prhash(unsigned char *h, int n)
Definition dcp.cpp:550
FLASHMEM void DCP_HASH_Finish(dcp_hash_ctx_t *ctx, uint8_t *output)
Definition dcp.cpp:493
struct utils::_dcp_handle dcp_handle_t
_dcp_work_packet_bit_definitions
Definition dcp.cpp:118
@ kDCP_CONTROL0_ENABLE_HASH
Definition dcp.cpp:120
@ kDCP_CONTROL1_HASH_SELECT_CRC32
Definition dcp.cpp:125
@ kDCP_CONTROL0_HASH_INIT
Definition dcp.cpp:121
@ kDCP_CONTROL1_HASH_SELECT_SHA1
Definition dcp.cpp:124
@ kDCP_CONTROL0_DECR_SEMAPHOR
Definition dcp.cpp:119
@ kDCP_CONTROL1_HASH_SELECT_SHA256
Definition dcp.cpp:123
@ kDCP_CONTROL0_HASH_TERM
Definition dcp.cpp:122
static FLASHMEM uint32_t dcp_hash_update_non_blocking(dcp_hash_ctx_internal_t *ctxInternal, dcp_work_packet_t *dcpPacket, const uint8_t *msg, size_t size)
Definition dcp.cpp:391
FLASHMEM void hash(const uint8_t *msg, size_t msg_len, uint8_t *out_hash, dcp_hash_algo_t algo)
Definition dcp.cpp:611
_dcp_ch_enable
Definition dcp.cpp:70
@ kDCP_ch1Enable
DCP channel 1 enable.
Definition dcp.cpp:73
@ kDCP_ch2Enable
DCP channel 2 enable.
Definition dcp.cpp:74
@ kDCP_chDisable
DCP channel disable.
Definition dcp.cpp:71
@ kDCP_ch0Enable
DCP channel 0 enable.
Definition dcp.cpp:72
@ kDCP_chEnableAll
DCP channel enable all.
Definition dcp.cpp:76
@ kDCP_ch3Enable
DCP channel 3 enable.
Definition dcp.cpp:75
static FLASHMEM uint32_t dcp_schedule_work(dcp_handle_t *handle, dcp_work_packet_t *dcpPacket)
Definition dcp.cpp:331
_dcp_hash_algo_state
Definition dcp.cpp:137
@ kDCP_StateHashUpdate
Update state.
Definition dcp.cpp:139
@ kDCP_StateHashInit
Init state.
Definition dcp.cpp:138
static FLASHMEM void dcp_reverse_and_copy(uint8_t *src, uint8_t *dest, size_t src_len)
Definition dcp.cpp:248
struct utils::_dcp_hash_ctx_internal dcp_hash_ctx_internal_t
_dcp_key_slot
Definition dcp.cpp:86
@ kDCP_KeySlot3
DCP key slot 3.
Definition dcp.cpp:90
@ kDCP_KeySlot2
DCP key slot 2.
Definition dcp.cpp:89
@ kDCP_PayloadKey
DCP payload key.
Definition dcp.cpp:93
@ kDCP_KeySlot0
DCP key slot 0.
Definition dcp.cpp:87
@ kDCP_OtpUniqueKey
DCP unique OTP key.
Definition dcp.cpp:92
@ kDCP_KeySlot1
DCP key slot 1.
Definition dcp.cpp:88
@ kDCP_OtpKey
DCP OTP key.
Definition dcp.cpp:91
struct utils::_dcp_work_packet dcp_work_packet_t
enum utils::_dcp_hash_algo_t dcp_hash_algo_t
FLASHMEM void hash_sha1(const uint8_t *msg, size_t msg_len, uint8_t *out_hash)
Computes the SHA1 sum of an arbitrary message (large memory segment), hardware-accelerated on the Tee...
Definition dcp.cpp:635
FLASHMEM void DCP_HASH_Init(dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo)
Definition dcp.cpp:452
void dcp_hash_update(dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *msg, size_t size)
Definition dcp.cpp:412
static FLASHMEM void dcp_clear_status()
Definition dcp.cpp:291
FLASHMEM void hash_sha256(const uint8_t *msg, size_t msg_len, uint8_t *out_hash)
Computes the SHA256 sum of an arbitrary message (large memory segment).
Definition dcp.cpp:631
enum utils::_dcp_channel dcp_channel_t
_dcp_swap
Definition dcp.cpp:96
@ kDCP_NoSwap
Definition dcp.cpp:97
@ kDCP_InputWordSwap
Definition dcp.cpp:101
@ kDCP_KeyByteSwap
Definition dcp.cpp:98
@ kDCP_InputByteSwap
Definition dcp.cpp:100
@ kDCP_OutputByteSwap
Definition dcp.cpp:102
@ kDCP_KeyWordSwap
Definition dcp.cpp:99
@ kDCP_OutputWordSwap
Definition dcp.cpp:103
FLASHMEM void demo_sha256()
Definition dcp.cpp:561
_dcp_channel
Definition dcp.cpp:79
@ kDCP_Channel3
DCP channel 3.
Definition dcp.cpp:83
@ kDCP_Channel2
DCP channel 2.
Definition dcp.cpp:82
@ kDCP_Channel1
DCP channel 1.
Definition dcp.cpp:81
@ kDCP_Channel0
DCP channel 0.
Definition dcp.cpp:80
FLASHMEM void demo_crc32()
Definition dcp.cpp:585
static FLASHMEM void dcp_clear_channel_status(uint32_t mask)
Definition dcp.cpp:296
union utils::_dcp_hash_block dcp_hash_block_t
FLASHMEM void dcp_hash_process_message_data(dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *message, size_t messageSize)
Definition dcp.cpp:426
struct utils::_dcp_hash_ctx_t dcp_hash_ctx_t
_dcp_hash_algo_t
Definition dcp.cpp:106
@ kDCP_Sha1
SHA_1.
Definition dcp.cpp:107
@ kDCP_Crc32
CRC_32.
Definition dcp.cpp:109
@ kDCP_Sha256
SHA_256.
Definition dcp.cpp:108
enum utils::_dcp_hash_algo_state dcp_hash_algo_state_t
_dcp_hash_digest_len
Definition dcp.cpp:112
@ kDCP_OutLenSha1
Definition dcp.cpp:113
@ kDCP_OutLenSha256
Definition dcp.cpp:114
@ kDCP_OutLenCrc32
Definition dcp.cpp:115
enum utils::_dcp_ch_enable _dcp_ch_enable_t
DCP - Register Layout Typedef.
Definition dcp.cpp:174
volatile uint32_t KEYDATA
DCP key data, offset: 0x70.
Definition dcp.cpp:189
volatile uint32_t CH2STAT
DCP channel 2 status register, offset: 0x1A0.
Definition dcp.cpp:225
volatile uint32_t CH3OPTS
DCP channel 3 options register, offset: 0x1F0.
Definition dcp.cpp:235
volatile uint32_t CH1CMDPTR
DCP channel 1 command pointer address register, offset: 0x140.
Definition dcp.cpp:213
volatile uint32_t CTRL
DCP control register 0, offset: 0x0.
Definition dcp.cpp:175
volatile uint32_t PACKET3
DCP work packet 3 status register, offset: 0xB0.
Definition dcp.cpp:197
volatile uint32_t CH1SEMA
DCP channel 1 semaphore register, offset: 0x150.
Definition dcp.cpp:215
volatile uint32_t PACKET0
DCP work packet 0 status register, offset: 0x80.
Definition dcp.cpp:191
volatile uint32_t PACKET4
DCP work packet 4 status register, offset: 0xC0.
Definition dcp.cpp:199
volatile uint32_t CH0SEMA
DCP channel 0 semaphore register, offset: 0x110.
Definition dcp.cpp:207
volatile uint32_t CAPABILITY1
DCP capability 1 register, offset: 0x40.
Definition dcp.cpp:183
volatile uint32_t CH2OPTS
DCP channel 2 options register, offset: 0x1B0.
Definition dcp.cpp:227
volatile uint32_t CH3SEMA
DCP channel 3 semaphore register, offset: 0x1D0.
Definition dcp.cpp:231
volatile uint32_t CH1STAT
DCP channel 1 status register, offset: 0x160.
Definition dcp.cpp:217
volatile uint32_t CH0OPTS
DCP channel 0 options register, offset: 0x130.
Definition dcp.cpp:211
volatile uint32_t CONTEXT
DCP context buffer pointer, offset: 0x50.
Definition dcp.cpp:185
volatile uint32_t CH3CMDPTR
DCP channel 3 command pointer address register, offset: 0x1C0.
Definition dcp.cpp:229
volatile uint32_t KEY
DCP key index, offset: 0x60.
Definition dcp.cpp:187
volatile uint32_t CH2CMDPTR
DCP channel 2 command pointer address register, offset: 0x180.
Definition dcp.cpp:221
volatile uint32_t VERSION
DCP version register, offset: 0x430.
Definition dcp.cpp:243
volatile uint32_t PACKET5
DCP work packet 5 status register, offset: 0xD0.
Definition dcp.cpp:201
volatile uint32_t CH0STAT
DCP channel 0 status register, offset: 0x120.
Definition dcp.cpp:209
volatile uint32_t PACKET6
DCP work packet 6 status register, offset: 0xE0.
Definition dcp.cpp:203
volatile uint32_t CAPABILITY0
DCP capability 0 register, offset: 0x30.
Definition dcp.cpp:181
volatile uint32_t CH1OPTS
DCP channel 1 options register, offset: 0x170.
Definition dcp.cpp:219
volatile uint32_t CH0CMDPTR
DCP channel 0 command pointer address register, offset: 0x100.
Definition dcp.cpp:205
volatile uint32_t CH2SEMA
DCP channel 2 semaphore register, offset: 0x190.
Definition dcp.cpp:223
volatile uint32_t PACKET2
DCP work packet 2 status register, offset: 0xA0.
Definition dcp.cpp:195
volatile uint32_t PAGETABLE
DCP page table register, offset: 0x420.
Definition dcp.cpp:241
volatile uint32_t DBGDATA
DCP debug data register, offset: 0x410.
Definition dcp.cpp:239
volatile uint32_t CH3STAT
DCP channel 3 status register, offset: 0x1E0.
Definition dcp.cpp:233
volatile uint32_t DBGSELECT
DCP debug select register, offset: 0x400.
Definition dcp.cpp:237
volatile uint32_t STAT
DCP status register, offset: 0x10.
Definition dcp.cpp:177
volatile uint32_t PACKET1
DCP work packet 1 status register, offset: 0x90.
Definition dcp.cpp:193
volatile uint32_t CHANNELCTRL
DCP channel control register, offset: 0x20.
Definition dcp.cpp:179
uint32_t swapConfig
For configuration of key, input, output byte/word swap options.
Definition dcp.cpp:146
dcp_key_slot_t keySlot
For operations with key (such as AES encryption/decryption), specify DCP key slot.
Definition dcp.cpp:145
uint32_t iv[4]
Definition dcp.cpp:148
dcp_channel_t channel
Specify DCP channel.
Definition dcp.cpp:143
uint32_t keyWord[4]
Definition dcp.cpp:147
dcp_hash_block_t blk
memory buffer.
Definition dcp.cpp:152
dcp_hash_algo_t algo
selected algorithm from the set of supported algorithms
Definition dcp.cpp:154
dcp_hash_algo_state_t state
finite machine state of the hash software process
Definition dcp.cpp:155
uint32_t fullMessageSize
track message size
Definition dcp.cpp:156
dcp_handle_t * handle
Definition dcp.cpp:159
uint32_t ctrl0
HASH_INIT and HASH_TERM flags.
Definition dcp.cpp:157
size_t blksz
number of valid bytes in memory buffer
Definition dcp.cpp:153
uint32_t runningHash[9]
running hash.
Definition dcp.cpp:158
uint32_t x[58]
Definition dcp.cpp:129
uint32_t destinationBufferAddress
Definition dcp.cpp:167
uint32_t payloadPointer
Definition dcp.cpp:169
uint32_t sourceBufferAddress
Definition dcp.cpp:166
uint32_t nextCmdAddress
Definition dcp.cpp:163
uint8_t b[128]
byte array
Definition dcp.cpp:134
uint32_t w[128/4]
array of 32-bit words
Definition dcp.cpp:133